반도체디스플레이기술학회지 (Journal of the Semiconductor & Display Technology)

한국반도체디스플레이기술학회 (The Korean Society Of Semiconductor & Display Technology)
권호 표지

고속 ATE 시스템을 위한 임피던스 정합회로 구현

Implementation of Impedance Matching Circuit for ATE

  • 김종원 (한국기술교육대학교 전기전자공학과) ;
  • 서용배 (한국 폴리텍 제 4 대학) ;
  • 이용성 (한국 폴리텍 제 2 대학)
  • Kim, Jong-Won (Depart of Electric and Electronics Eng, Korea University of Technology and Education) ;
  • Seo, Yong-Bae (Depart of Electronic Communication, Korea Polytechnic VI Collage) ;
  • Lee, Yong-Sung (Depart of Electronic Communication, Korea Polytechnic II Collage)
  • 발행 : 2006.12.31
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초록

In the manufacturing processes of semiconductor, test process is important for quality of products. In the manufacturing process of dynamic memory, memory test is more important. So, automatic test equipment(ATE) is used necessarily. But, according to increase of speed of dynamic memory operation, the rapid test equipment is needed. Impedance matching between ATE and dynamic memory is expected to be an important problem for making a rapid test equipment over 1Gbps. According to increase of speed, inner impedance of ATE also works on important parameter for test. This paper is about the method that is for impedance matching of inner impedance and coaxial cable occurring in manufacturing of ATE. We proved effects of inner impedance by electric theory and verified the method of impedance matching using computer simulation.

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