대한전자공학회논문지SD (Journal of the Institute of Electronics Engineers of Korea SD)

대한전자공학회 (The Institute of Electronics and Information Engineers)
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결합 커패시턴스의 영향을 고려한 CMOS 셀 구동 모델

A CMOS Cell Driver Model to Capture the Effects of Coupling Capacitances

  • 조경순 (한국외국어대학교 전자정보공학부)
  • Cho, Kyeong-Soon (Department of Electronics and Information Engineering, Hankuk University of Foreign Studies)
  • 발행 : 2005.11.01
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초록

미세 선 폭을 갖는 반도체 칩에서 관찰할 수 있는 crosstalk 효과는 배선 회로 사이에 존재하는 결합 커패시턴스에 의한 현상이다. 칩 전체에 대한 타이밍 분석의 정확도는 칩을 구성하는 셀과 배선에 대한 지연시간 예측 자료의 정확도에 의해서 결정된다. 본 논문에서는 결합 커패시턴스에 의한 crosstalk 효과를 반영하여 지연시간을 정확하고 효율적으로 계산할 수 있는 CMOS 셀 구동 모델과 관련 알고리즘을 제안하고 있다. 제안한 모델과 알고리즘을 지연시간 계산 프로그램에 구현하고, 칩 레이아웃에서 추출한 벤치마크회로에 대한 지연시간 예측에 적용하였다. Victim에 영향을 주는 Aggressor를 $0\~10$개까지 연결하여 각각의 경우에 대한 셀 및 배선의 지연시간을 HSPICE와 비교한 결과 $1\%$ 내외의 오차를 보이는 우수한 정확도를 확인하였다.

The crosstalk effects that can be observed in the very dee submicron semiconductor chips are due to the coupling capacitances between interconnect lines. The accuracy of the full-chip timing analysis is determined by the accuracy of the estimated propagation delays of cells and interconnects within the chip. This paper presents a CMOS cell driver model and delay calculation algerian capturing the crosstalk effects due to the coupling capacitances. The proposed model and algorithm were implemented in a delay calculation program and used to estimate the propagation delays of the benchmark circuits extracted from a chip layout. We observed that the average discrepancy from HSPICE simulation results is within $1\%$ for the circuits with a victim affected by $0\~10$ aggressors.

키워드

참고문헌

  1. E. Y. Chung, B. H. Joo, Y. K. Lee, K. H. Kim and S. H. Lee, 'Advanced Delay Analysis Method for Submicron ASIC Technology,' Proc. of IEEE ASIC Seminar, pp. 471-474, 1992 https://doi.org/10.1109/ASIC.1992.270245
  2. J. Qian, S. Pullela and L. T. Pillage, 'Modeling the Effective Capacitance for the RC Interconnect of CMOS Gates,' IEEE Trans. on Computer-Aided Design, vol. 13, no. 12, pp. 1526-1535, December 1994 https://doi.org/10.1109/43.331409
  3. J. Rubinstein, P. Penfield Jr. and M. A. Horowitz, 'Signal Delay in RC Tree Networks,' IEEE Trans. on Computer-Aided Design, vol. 2, no. 3, pp. 202-211, July 1983 https://doi.org/10.1109/TCAD.1983.1270037
  4. L. T. Pillage and R. A. Rohrer, 'Asymptotic Waveform Evaluation for Timing Analysis,' IEEE Trans. on Computer-Aided Design, vol. 9, no. 4, pp. 352-366, April 1990 https://doi.org/10.1109/43.45867
  5. F. Dartu, N. Menezes and L. T. Pileggi, 'Performance Computation for Precharacterized CMOS Gates with RC Loads,' IEEE Trans. on Computer-Aided Design, vol. 15, no. 5, pp. 544-553, May 1996 https://doi.org/10.1109/43.506141
  6. F. Dartu and L. T. Pileggi, 'Calculating Worst-Case Gate Delays Due to Dominant Capacitance Coupling,' Proc. of Design Automation Conference, 1997 https://doi.org/10.1145/266021.266033
  7. 조경순, 변영기, 'CMOS 게이트에 의해서 구동되는 배선 회로의 타이밍 특성 분석,' 전자공학회논문지, 제35권 C편 제4호, pp. 21-29, April 1998
  8. P. D. Gross, R. Arunachalam, K. Rajagopal and L. T. Pileggi, 'Determination of Worst-Case Aggressor Alignment for Delay Calculation,' Proc. of International Conference on Computer-Aided Design, 1998 https://doi.org/10.1145/288548.288616
  9. B. N. Sheehan, 'Predicting Coupled Noise in RC Circuits by Matching 1, 2, and 3 Moments,' Proc. of Design Automation Conference, 2000 https://doi.org/10.1145/337292.337568
  10. T. Uchino and J. Cong, 'An Interconnet Energy Model Considering Coupling Effects,' Proc. of Design Automation Conference, 2001 https://doi.org/10.1145/378239.379022
  11. D. Blaauw, S. Sirichotiyakul and C. Oh, 'Driver Modeling and Alignment for Worst-Case Delay Noise,' IEEE Trans. on VLSI Systems, vol. 11, no. 2, pp. 157-166, April 2003 https://doi.org/10.1109/TVLSI.2002.808448
  12. B. Tutuianu, R. Baldick and M. Johnstone, 'Nonlinear Driver Models for Timing and Noise Analysis,' IEEE Trans. on Computer-Aided Design, vol. 23, no. 11, pp. 1510-1521, November 2004 https://doi.org/10.1109/TCAD.2004.835136