Journal of the Institute of Electronics Engineers of Korea SD (대한전자공학회논문지SD)

The Institute of Electronics and Information Engineers (대한전자공학회)
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Decoupling Capacitance Allocation at the Floorplan Level for Power Supply Noise Reduction

전원 잡음을 줄이기 위한 평면계획 단계에서의 Decoupling Capacitance 할당

  • Published : 2005.09.01
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Abstract

This paper proposes a method which efficiently allocates decoupling capacitance to reduce power supply noise at the floorplan level. We observe problems of previous approach that the decoupling capacitance of each module was overestimated and the power supply noises of modules were changed by inserting additional area for decoupling capacitance, and then suggest a new approach. And, we also present a simple heuristic method which can effectively allocate white space modules for decoupling capacitance area within more faster time instead of LP technique. Experimental results show that our approach can reduce the area of decoupling capacitance to average 7.9 percent compared with Zhao's approach in [4]. Therefore both total area and wire length of nniflm result are decreased. Also, we confirm that our approach solves well the problem caused by inserting additional area. In execution time comparison, our approach shows average 11.6 percent improvement.

본 논문에서는 평면계획 단계에서 모듈의 전원 잡음을 줄이기 위해 필요한 decoupling capacitance를 효과적으로 할당하는 방법을 제시한다. 먼저, 각 모듈의 decoupling capacitance가 과대평가되고 추가 면적 삽입으로 모듈의 전원 잡음이 변하는 기존 접근 방법의 문제점을 살펴보고, 이를 해결할 수 있는 새로운 방법을 제시한다. 또한, 선형프로그래밍 방법보다 빠른 시간 내에 decoupling capacitance 면적을 위한 빈 공간을 할당하는 간단한 휴리스틱 방법을 제안한다. 실험결과에서 제시된 방법은 Zhao[4]의 방법과 비교하여 decoupling capacitance 면적이 평균 $7.9\%$ 감소하고, 이로 인해 평면계획 결과의 전체 면적과 와이어 길이가 감소하였다. 또한, 추가 면적 삽입으로 인한 모듈의 전원 잡음 문제를 잘 해결하고 있음을 확인하였다. 수행시간 비교에서는 평균 $11.6\%$의 향상을 보였다.

Keywords

References

  1. H. Bakoglu, 'Circuits, Interconnections, and Packaging for VLSI,' Addison-Wesley, 1990
  2. H. H. Chen and D. D. Ling, 'Power Supply Noise Analysis Methodology for Deep-Submicron VLSI Chip Design,' in Proc. IEEE/ACM Design Automation Corference, pp. 638-643, 1997
  3. H. Su, S. S. Sapatnekar and S. R. Nassif, 'An Algorithm for Optimal Decoupling Capacitor Sizing and Placement for Standard Cell Layouts,' in Proc. IEEE/ACM International Symposium on Physical Design, pp. 68-73, 2002 https://doi.org/10.1145/505388.505405
  4. S. Zhao, K. Roy and C. K. Koh, 'Decoupling Capacitance Allocation and Its Application to Power Supply Noise-Aware Floorplanning,' IEEE Trans. on Computer Aided Design of Integrated Circuits and Systems, vol. 21, pp. 81-92, Jan. 2002 https://doi.org/10.1109/43.974140
  5. L. Smith, 'Decoupling Capacitor Calculation for CMOS Circuits,' in Proc. IEEE 3rd Topical Meeting of Electrical Performance of Electronic Packaging, pp. 101-105, 1994 https://doi.org/10.1109/EPEP.1994.594099
  6. G. Bai, S. Bobba and I. N. Hajj, 'Simulation and Optimization of the Power Distribution Network in VLSI Circuits,' in Proc. IEEE/ACM International Conference on Computer Aided Design, pp. 481-486, 2000
  7. T. Wang and C. C. Chen, 'Optimization of the Power/Ground Network Wire-Sizing and Spacing Based on Sequential Network Simplex Algorithm,' in Proc. IEEE International Symposium on Quality Electronic Design, pp. 157-162, 2002
  8. J. Singh and S. S. Sapatnekar, 'Topology Optimization of Structured Power/Ground Networks,' in Proc. IEEE/ACM International Symposium on Physical Design, pp. 116-119, 2004 https://doi.org/10.1145/981066.981093
  9. X. Hong, G. Huang, Y. Cai, J. Gu, S. Dong, C. K. Cheng and J. Gu, 'Corner Block List : An Effective and Efficient Topological Representation of Non-Slicing Floorplan,' in Proc. IEEE/ACM Internation Conference on Computer Aided Design, pp. 8-12, 2000 https://doi.org/10.1109/ICCAD.2000.896442
  10. S. Zhou, S. Dong, X. Hong, Y. Cai, C. K. Cheng and J. Gu, 'ECBL : An Exteneded Corner Block List with Solution Space Including Optimum Placement,' in Proc. IEEE/ACM International Symposium on Physical Design, 2001
  11. H. Murata, K. Fujiyoshi, S. Nakatake and Y. Kajitani, 'Rectangle Packing Based Module Placement,' in Proc. IEEE/ACM International Conference on Computer Aided Design, pp. 472-479, 1995 https://doi.org/10.1109/ICCAD.1995.480159
  12. X. Tang, R. Tian and D. F. Wong, 'Fast Evaluation of Sequence Pair in Block Placement by Longest Common Subsequence Computation,' in Proc. Design Automation Test Eur., pp. 100-111, 2000 https://doi.org/10.1109/DATE.2000.840024
  13. T. H. Chen and C. C. P. Chen, 'Efficient Large-Scale Power Grid Analysis Based on Preconditioned Krylov-Subspace Iterative Methods,' in Proc. IEEE/ACM Design Automation Conference, pp. 559-562, 2001 https://doi.org/10.1145/378239.379023
  14. S. Zhao, K. Roy and C. K. Koh, 'Estimation of Inductive and Resistive Switching Noise on Power Supply Network in Deep Sub-micron CMOS Circuits,' in Proc. IEEE International Conference on Computer Design, pp. 65-72, 2000 https://doi.org/10.1109/ICCD.2000.878270
  15. H. Li, Z. Qi, S. X.-D. Tan, L. Wu, Y. Cai and X. Hong, 'Partitioning-Based Approach to Fast On-Chip Decap Budgeting and Minimization,' in Proc. IEEE/ACM Design Added Conference, pp. 170-175, 2005
  16. International Technology Roadmap for Semiconductor, Semiconductor Industry Association, 1997