대한전자공학회논문지SD (Journal of the Institute of Electronics Engineers of Korea SD)

대한전자공학회 (The Institute of Electronics and Information Engineers)
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새로운 가변 Degeneration 저항을 사용한 2.5V 300MHz 80dB CMOS VGA 설계

Design of a 2.5V 300MHz 80dB CMOS VGA Using a New Variable Degeneration Resistor

  • 발행 : 2003.09.01
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⟨ 이전 논문 다음 논문 ⟩

초록

디지털 신호에 의해 이득이 조절되는 CMOS VGA의 구조로는 degenerated 차동쌍 구조가 많이 사용되고 있다. 이 구조에서 가변 degeneration 저항을 구현하기 위해 기존해 사용되던 방법으로는 MOSFET 스위치와 함께 저항열 구조를 사용하는 방법과 R-2R ladder 구조를 사용하는 방법이 있다. 그러나 이 방법들을 이용하는 경우에는 degeneration 저항에서의 dc 전압 강하에 의해 저전압 동작이 어려우며, 높은 이득 설정시 대역폭이 크게 제한되기 때문에 고속의 VGA 구현이 어렵다. 따라서, 본 논문에서는 이러한 문제점들을 해결하기 위해 degeneration 저항에서의 dc 전압 강하를 제거한 새로운 가변 degeneration 저항을 제안하였다. 제안된 이득조절 방법을 사용하여, 저전압에서 동작하는 고속의 CMOS VGA를 설계하였다. 0.2㎛ CMOS 공정변수를 사용하여 HSPICE 모의실험을 한 결과, 설계된 VGA는 360MHz의 대역폭과 80dB의 이득조절 범위를 갖는다. 이득오차는 200MHz에서 0.4dB보다 작으며 300MHz에서는 1.4dB보다 작다. 설계된 회로는 2.5V의 전원전압에서 10.8mA의 전류를 소모하며, 칩 면적은 1190㎛×360㎛이다.

A degenerated differential pair has been widely used as a standard topology for digitally programmable CMOS VGAs. A variable degeneration resistor has been implemented using a resistor string or R-2R ladder with MOSFET switches. However, in the VGAs using these conventional methods, low-voltage and high-speed operation is very hard to achieve due to the dc voltage drop over the degeneration resistor. To overcome this problem a new variable degeneration resistor is proposed where the dc voltage drop is almost removed. Using the proposed gain control scheme, a low-voltage and high-speed CMOS VGA is designed. HSPICE simulation results using a 0.25${\mu}{\textrm}{m}$ CMOS process parameters show that the designed VGA provides a 3dB bandwidth of 360MHz and a 80dB gain control range in 2dB step. Gain errors are less than 0.4dB at 200MHz and less than l.4dB at 300MHz. The designed circuit consumes 10.8mA from a 2.5V supply and its die area is 1190${\mu}{\textrm}{m}$${\times}$360${\mu}{\textrm}{m}$.

키워드

참고문헌

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