• Title/Summary/Keyword: degenerated 차동쌍

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Design of a 2.5V 300MHz 80dB CMOS VGA Using a New Variable Degeneration Resistor (새로운 가변 Degeneration 저항을 사용한 2.5V 300MHz 80dB CMOS VGA 설계)

  • 권덕기;문요섭;김거성;박종태;유종근
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.40 no.9
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    • pp.673-684
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    • 2003
  • A degenerated differential pair has been widely used as a standard topology for digitally programmable CMOS VGAs. A variable degeneration resistor has been implemented using a resistor string or R-2R ladder with MOSFET switches. However, in the VGAs using these conventional methods, low-voltage and high-speed operation is very hard to achieve due to the dc voltage drop over the degeneration resistor. To overcome this problem a new variable degeneration resistor is proposed where the dc voltage drop is almost removed. Using the proposed gain control scheme, a low-voltage and high-speed CMOS VGA is designed. HSPICE simulation results using a 0.25${\mu}{\textrm}{m}$ CMOS process parameters show that the designed VGA provides a 3dB bandwidth of 360MHz and a 80dB gain control range in 2dB step. Gain errors are less than 0.4dB at 200MHz and less than l.4dB at 300MHz. The designed circuit consumes 10.8mA from a 2.5V supply and its die area is 1190${\mu}{\textrm}{m}$${\times}$360${\mu}{\textrm}{m}$.

A New Variable Degeneration Resistor for Digitally Programmable CMOS VGA (디지털 방식의 이득조절 기능을 갖는 CMOS VGA를 위한 새로운 가변 축퇴 저항)

  • Kwon, Duck-Ki;Park, Jong-Tae;Yu, Chong-Gun
    • Journal of IKEEE
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    • v.7 no.1 s.12
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    • pp.43-55
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    • 2003
  • A degenerated differential pair has been widely used as a standard topology for digitally programmable CMOS VGAs. A variable degeneration resistor has been implemented using a resistor string or R-2R ladder with MOSFET switches. However, in the VGAs using these conventional methods, low-voltage and high-speed operation is very hard to achieve due to the dc voltage drop over the degeneration resistor. To overcome the problem a new variable degeneration resistor is proposed where the dc voltage drop is almost removed. The proposed gain control scheme makes it easy to implement a low-voltage and high-speed VGA. This paper describes the problems existed in conventional methods, the principle and advantages of the proposed scheme, and their performance comparison in detail. A CMOS VGA cell is designed using the proposed degeneration resistor. The 3dB bandwidths are greater than 650㎒ and the gain errors are less than 0.3dB in a gain control range from -12dB to +12dB in 6dB steps. It consumes 3.1㎃ from a 2.5V supply voltage.

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