• 제어로봇시스템학회:학술대회논문집
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• 2005.06a
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• pp.792-793
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• 2005

Circuit testing process is very important in IC Manufacturing there are two ways in research for circuit testing improvement. These are ATPG Tool Design and Test simulation application. We are interested in how to use parallel technique such as one-side communication, parallel IO and dynamic Process with data partition for circuit testing improvement and we use one-side communication technique in this paper. The parallel ATPG Tool can reduce the test pattern sets of the circuit that is designed in laboratory for make sure that the fault is not occur. After that, we use result for parallel circuit test simulation to find fault between designed circuit and tested circuit. From the experiment, We use less execution time than non-parallel Process. And we can set more parameter for less test size. Previous experiment we can't do it because some parameter will affect much waste time. But in the research, if we use the best ATPG Tool can optimize to least test sets and parallel circuit testing application will not work. Because there are too little test set for circuit testing application. In this paper we use a standard sequential circuit of ISCAS89.

• Proceedings of the KIEE Conference
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• 2001.07e
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• pp.134-140
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• 2001

Parallel processing has the potential to be cost effectively used on computationally intense power system problems. But this technology is not still available is not only parallel computer but also parallel processing scheme. Testing these algorithms to ensure accuracy, and evaluation of their performance is also an issue. Although a significant amount of parallel algorithms of power system problem have been developed in last decade, actual testing on processor architectures lies in the beginning stages. This paper presents the parallel processing algorithm to supply the base being able to treat power flow by newton's method by the distributed memory type parallel computer. This method is to assign and to compute teared blocks of sparse matrix at each parallel processors. The testing to insure accuracy of developed method have been done on serial computer by trying to simulate a parallel environment.

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.51 no.2
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• pp.55-59
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• 2002

Parallel processing is able to be used effectively on computationally intense power system problems. But this technology is not still available is not only parallel computer but also parallel processing scheme. Testing these algorithms to ensure accuracy, and evaluation of their performance is also an issue. Although a significant amount of parallel algorithms of power system problem have been developed in last decade, actual testing on parallel computer architectures lies in the beginning stages because no clear cut paths. This paper presents Jacobian modeling method to supply the base being able to treat power flow by newton's method by the computer. This method is to assign and to compute teared blocks of sparse matrix at each parallel processors. The testing to insure accuracy of developed method have been done on serial computer by trying to simulate a parallel environment.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.11
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• pp.130-138
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• 2016

In this paper present the real-time system parallel testing techniques for weapon systems error verification. Previously field testing equipment in the military field was using the sequential testing method to maintain. This method could not check the error verification of interference. For this reason, in this paper propose the real-time system parallel testing techniques using an embedded module instead of the sequential testing techniques which is used in the weapon system error verification. Using the embedded module mounted switching control card conduct the parallel testing and then send the result to the PC. This method is possible to increase the reliability in the weapon system error verification.

• Journal of the Korean Society of Industry Convergence
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• v.14 no.2
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• pp.79-85
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• 2011

This study has been experimented about refrigeration capacity difference. It has been used 3 method, Manual expansion valve, thermostatic expansion valve and capillary expansion valve, and tested under the same condition by using the performance testing of parallel expansion. In temperature change of the temperature room, thermostatic expansion valve method displayed the most lower temperature, $-18^{\circ}C$. In addition, the temperature, just before the expansion, also displayed the best result which was $4^{\circ}C$ lower than other expansion valve. In these results, it can be used for performance testing of parallel expansion refrigeration system.

• Proceedings of the Computational Structural Engineering Institute Conference
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• 2003.04a
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• pp.521-528
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• 2003

This paper presents the results of a cooperative research on remote parallel pseudo-dynamic testing on a base-isolated bridge with multiple piers using Internet between KAIST, Korea and Kyoto Univ., Japan. Experimental facilities located at two institutions were parallelly used to test the nonlinear behavior of the base-isolators. Two data communication schemes for parallel tests were developed and the performance is compared. The results indicate that the elapsed time may vary widely depending on the data communication and testing schemes : i.e. 1-25sec for each time step. But it is fairly comparable with the time required for pseudo-dynamic testing. The testing method can become more powerful, as the data communication and monitoring techniques through Internet improve further.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.33 no.9
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• pp.982-989
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• 2009

Parallel Kinematic Mechanism (PKM) is a device to perform the various motion in three-dimensional space and it calls for six degree of freedom. For example, Parallel Kinematic Mechanism is applied to machine tools, medical equipments, MEMS, virtual reality devices and flight motion simulators. Recently, many companies have tried to develop new Parallel Kinematic Mechanism in order to improve the cycle time and the precisional tolerance. Parallel Kinematic Mechanism uses general universal joint and spherical joint, but such joints have accumulated tolerance problems. Therefore, it causes position control problem and dramatically life time reduction. This paper focused on the rolling element to improve sliding precision in new sliding ball joint development. Before the final design and production, it was confirmed that new sliding ball joint held a higher load and a good geometrical structure. FEM analysis showed a favorable agreement with tensile and compressive testing results by universal testing machine. In conclusions, a new sliding ball joint has been developed to solve a problem of accumulated tolerance and verified using tensile and compressive testing as well as FEM analysis.

• Genomics & Informatics
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• v.20 no.1
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• pp.14.1-14.4
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• 2022

Permutation testing is a robust and popular approach for significance testing in genomic research that has the advantage of reducing inflated type 1 error rates; however, its computational cost is notorious in genome-wide association studies (GWAS). Here, we developed a supercomputing-aided approach to accelerate the permutation testing for GWAS, based on the message-passing interface (MPI) on parallel computing architecture. Our application, called MPI-GWAS, conducts MPI-based permutation testing using a parallel computing approach with our supercomputing system, Nurion (8,305 compute nodes, and 563,740 central processing units [CPUs]). For 10⁷ permutations of one locus in MPI-GWAS, it was calculated in 600 s using 2,720 CPU cores. For 10⁷ permutations of ~30,000-50,000 loci in over 7,000 subjects, the total elapsed time was ~4 days in the Nurion supercomputer. Thus, MPI-GWAS enables us to feasibly compute the permutation-based GWAS within a reason-able time by harnessing the power of parallel computing resources.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.68 no.2
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• pp.364-369
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• 2019

Generally, since memory chips should be tested all, considering its volume, the reduction in test time for detecting faults plays an important role in reducing the overall production cost. The parallel testing of chips in one ATE is a competitive solution to solve it. In this paper, NOC is proposed as test interface architecture between DUTs and ATE. Because NOC can be extended freely, there is no limit on the number of DUTs tested at the same time. Thus, more memory can be tested with the same bandwidth of ATE. Furthermore, the proposed NOC-based parallel test method can increase the efficiency of channel usage by packet type data transmission.

• Proceedings of the Computational Structural Engineering Institute Conference
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• 2000.04b
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• pp.304-307
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• 2000

This paper presents a numerical simulation study for remote parallel pseudo-dynamic testings using Internet. In this testing method, experimental facilities located at different places can be parallelly used for testing a large-scale structure with many components subjected to severe nonlinear behavior. Example analysis is carried out on a base- isolated bridge for earthquake loading. The results indicate that the time required for data communication between two facilities located 250km apart through Internet for t 000 time steps is about 20 minutes, which is fairly equivalent to the time required for pseudo-dynamic testing. This testing method can be more powerful, as the data transmitting technique through Internet improves.