The Transactions of the Korean Institute of Electrical Engineers D (대한전기학회논문지:시스템및제어부문D)

The Korean Institute of Electrical Engineers (대한전기학회)
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A Design of Instruction Based Wrapped Core Linking Module for Hierarchical SoC Test Access

계층적 SoC 테스트 접근을 위한 명령어 기반 코아 연결 모듈의 설계

  • 이현빈 (한양대 공학대 컴퓨터공학과) ;
  • 박성주 (한양대 공학대 전자컴퓨터공학부)
  • Published : 2003.03.01
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Abstract

For a System-on-a-Chip(SoC) comprised of multiple IP cores, various design techniques have been proposed to provide diverse test link configurations. In this paper, we introduce a new instruction based Wrapped Core Linking Module(WCLM) that enables systematic integration of IEEE 1149.1 TAP'd cotes and P1500 wrapped cores with requiring least amount of area overhead compared with other state-of-art techniques. The design preserves compatibility with standards and scalability for hierarchical access.

Keywords

References

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