대한전기학회논문지:전기물성ㆍ응용부문C (The Transactions of the Korean Institute of Electrical Engineers C)

대한전기학회 (The Korean Institute of Electrical Engineers)
권호 표지

CMOS 그라운드 연결망에서의 최대 동시 스위칭 잡음의 해석 모형

An Analytical Model of Maximum Simultaneous Switching Noise for Ground Interconnection Networks in CMOS Systems

  • 발행 : 2001.03.01
PDF 다운로드
⟨ 이전 논문 다음 논문 ⟩

초록

This paper presents an efficient and simple method for analyzine maximum simultaneous switching noise (SSN) on ground interconnection networks in CMOS systems. For the derivation of maximum SSN expression, we use ${\alpha}$-power law MOS model and Taylor's series approximation. The accuracy of the proposed method is verified by comparing the results with those of previous researches and HSPICE simulations under the contemporary process parameters and environmental conditions. The proposed method predicts the maximum SSN values more accurately when compared to existing approaches even in most practical cases such that exist some output drivers not in transition.

키워드

참고문헌

  1. A. J. Rainal, 'Computing inductive noise of chip packages,' AT&T Bell Labs Tech. J.. vol. 63, pp. 177-195, Jan. 1984
  2. G. Katopis, '$\Delta$I noise specification for a high performance computer machine,' Proc. IEEE, Sept. 1985, vol. 73, pp. 1405-1415
  3. R. Senthinathan and J. L. Prince, 'Simultaneous switching ground noise calculation for packaged CMOS devices,' IEEE J. Solid-State Circuits, vol. 26, pp, 1724-1728, Nov. 1991 https://doi.org/10.1109/4.98995
  4. A. Vaidyanath, B. Thoroddsen, and J. L. Prince, 'Effect of CMOS driver loading conditions on simultaneous switching noise,' IEEE Trans. Comp., Packag., Manufact. Technol. B, vol. 17, pp. 480-485, Nov. 1994 https://doi.org/10.1109/96.338712
  5. S. R. Vemuru, 'Accurate simultaneous switching noise estimation including velocity-saturation effect,' IEEE Trans. Comp., Packag., Manufact. Technol. B, vol. 19, pp. 344-349, May 1996 https://doi.org/10.1109/96.496038
  6. T. Sakurai and A. Newton, 'Alpha-power law MOSFET model and its applications to CMOS inverter delay and other formulations,' IEEE J. Solid-State Circuits, vol. 25, pp. 584-594, Apr. 1990 https://doi.org/10.1109/4.52187
  7. Hye-Ran cha and Oh-Kyong Kwon, 'An analytical model simultaneous switching noise in CMOS systems,' IEEE Transactions on Advanced Packaging, vol. 23, No.1, Feb. 2000 https://doi.org/10.1109/6040.826763
  8. Chender Huang, Yaochao Yang, and John L. Prince, 'A Simultaneous Switching Noise Design Algorithm for Leadframe Packages with or without Ground Plane,' IEEE Trans. on Components, Packaging, and Manufacturing Tech., Part B, vol. 19, No. 1, Feb 1996 https://doi.org/10.1109/96.486478
  9. Lei Lin and John L. Prince, 'SSO Noise Electrical Performance Limitations for PQFP Packages,' IEEE Trans. on Components, Packaging, and Manufacturing Tech.. Part B, vol. 20, No.3, Aug. 1997 https://doi.org/10.1109/96.618229
  10. William H. Press, Brian P. Flannery, Saul A. Teukolsky, William T. Vetterling, Numerical Recipes in C, Cambridge University Press, 1990. pp. 156-157
  11. Ramesh Senthinathan and John L. Prince, 'Simultaneous Switching Noise of CMOS Devices and Systems,' Kluwer Academic Publishers, 1994