패킷 방식의 DRAM에 적용하기 위한 새로운 강조 구동회로

A New Pre-Emphasis Driver Circuit for a Packet-Based DRAM

  • 김준배 (한양대 공대 전자전기컴퓨터공학부) ;
  • 권오경 (한양대 공대 전자전기컴퓨터공학부)
  • 발행 : 2001.04.01

초록

As the data rate between chip-to-chip gets high, the skin effect and load of pins deteriorate noise margin. With these, noise disturbances on the bus channel make it difficult for receiver circuits to read the data signal. This paper has proposed a new pre-emphasis driver circuit which achieves wide noise margin by enlarging the signal voltage range during data transition. When data is transferred from a memory chip to a controller, the output boltage of the driver circuit reaches the final values through the intermediate voltage level. The proposed driver supplies more currents applicable to a packet-based memory system, because it needs no additional control signal and realizes very small area. The circuit has been designed in a 0.18 ${\mu}m$ CMOS process, and HSPICE simulation results have shown that the data rate of 1.32 Gbps be achieved. Due to its result, the proposed driver can achieved higher speed than conventional driver by 10%.

키워드

참고문헌

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