Annealing Effects on $Q_{BD}$ of Ultra-Thin Gate Oxide Grown on Nitrogen Implanted Silicon

열처리 효과가 질소이온주입후에 성장시킨 산화막의 $Q_{BD}$ 특성에 미치는 영향

  • Nam, In-Ho (Dept.of Electronics Engineering, Seoul National University) ;
  • Hong, Seong-In (Dept.of Electronics Engineering, Seoul National University) ;
  • Sim, Jae-Seong (Dept.of Electronics Engineering, Seoul National University) ;
  • Park, Byeong-Guk (Dept.of Electronics Engineering, Seoul National University) ;
  • Lee, Jong-Deok (Dept.of Electronics Engineering, Seoul National University)
  • Published : 2000.03.01

Abstract

Ultra-thin gate oxide was grown on nitrogen implanted silicon substrates. For nitrogen implantation, the energy was fixed at 25keV, but the dose was split into 5.0$\times$10$^{13}$ /c $m^{2}$ and 1.0$\times$10$^{14}$ /c $m^{2}$. The grown gate oxide thickness were 2nm, 3nm and 4nm. The oxidation time to grow 3nm was increased by 20% and 50% for the implanted wafers of 5.0$\times$10$^{13}$ /c $m^{2}$ and 1.0$\times$10$^{14}$ /c $m^{2}$ doses, respectively, when it was compared with control wafers which were not implanted by nitrogen. The value of charge-to-breakdown ( $Q_{BD}$ ) is decreased with increasing nitrogen doses. If an annealing process( $N_{2}$, 85$0^{\circ}C$, 60min.) is peformed after nitrogen implantation, $Q_{BD}$ is increased. It is indicated that nitrogen implantation damage affect gate oxide reliability and the damage can be removed by post-implantation annealing process.

실리콘 기판에 질소를 이온주입한 다음에 게이트 산화막을 2nm, 3nm, 4nm 두께로 성장시켰다. 질소이온주입 에너지는 25keV로 고정하였고 이온주입량은 5.0×10/sup l3//cm/sup 2/과1.0×10/sup 14//cm/sup 2/으로 나누어서 진행하였다. 질소이온주입량과 산화막의 성장률은 밀접한 관계가 있으며 질소이온주입량이 많아지면 산화막의 성장시간이 늘어난다. 같은 두께를 기르는데 필요한 산화시간을 질소이온주입을 하지 않은 경우와 비교하면 질소이온 주입량이 5.0×10/sup 13//cm/sup 2/ 일 때는 약 20%, 1.0×10/sup 14//cm/sup 2/일 때는 약 50% 정도 산화시간이 증가한다. 질소이온 주입량이 증가함에 따라 Q/sub BD/값은 감소하는데 이의 개선을 위해 질소이온주입후에 N/sub 2/분위기에서 850℃ 60분간 열처리를 한 다음 산화막을 성장시키면 Q/sub BD/값이 증가하여 개선됨을 보인다. 이것은 질소이온주입으로 인한 손상이 게이트 산화막의 신뢰성에 나쁜 영향을 미치지만 이온주입직후에 적절한 열처리 공정을 거치면 이러한 손상으로 인한 영향을 없앨 수 있다는 것을 의미한다.

Keywords

References

  1. A.Uchiyama, H. Fukuda, T. Hayashi, T. Iwabuchi and S. Ohno, 'High performance dual-gate sub-halfmicron MOSFETs with 6nm-thick nitrided $SiO_2$ films in an $N_2O$ ambiend.' IEDM, p.425, 1990 https://doi.org/10.1109/IEDM.1990.237141
  2. Z. Ma, Z. H Liu, J. T. Krick, H. J. Huang, Y. C. Cheng, C. Hu and P. K. Ko, 'Optimization of gate oxide $N_2O$ anneal for CMOSFET's at room and cryogenic temperatures,' IEEE Trans. On Electron Devices 41, p 1364 , 1994 https://doi.org/10.1109/16.297731
  3. T. Ito, T. Nakamura, and H Ishikawa, 'Advantages of thermal nitride and nitroxide gate films in VLSI process,' IEEE Electron Devices, 29, p.498, 1982
  4. K. S. Krisch, L. Manchanda, F. H. Baumann, M. L. Green, D. Brasen, L. D. Fedman and A. Ourmazd, 'Impact of Boron Diffusion through $O_2$ and $N_2O$ Gate Dielectrics on the Process Margin of Dual-Poly Low Power CMOS,' IEDM, p.325,1994 https://doi.org/10.1109/IEDM.1994.383402
  5. H. hwang, W. Ting, D. L. Kwong and J. Lee, 'Electrical and reliability characteristics of ultrathin oxynitride gate dielectric prepared by rapid thermal processing in $N_2O,'$ IEDM, p.421, 1990 https://doi.org/10.1109/IEDM.1990.237142
  6. T. S. Chao, C. H. Chien, C. P. Hao, M. C. Liaw, C. H. Chu, C. Y. Chang and T. F. Lei, 'Mechanism and Optimization of Nitrogen Co-Implant for Suppressing Boron Penetration in P+-Poly-Si Gate of PMOSFET's,' SSDM, p.421, 1990
  7. C. T. Liu, Y. Ma. J. Becerro, S. Nakahara, D. J. Eaglesham and S. J. Hillenius, 'Preventing boron penetration throught 2.5nm gate oxides with nitrogen implant in the Si substrates,' IEEE Electron Device Letters 18, p.105, 1997 https://doi.org/10.1109/55.568768
  8. M. Bhat, D. Wristers, J. Yan, L. K. Han, J. Fulford and D. L. Kwong, 'Performance and Hot-Carrier Reliability of N- and P-MOSFETs with Rapid Thermally NO-nitrided SiO2 Gate Dielectrics,' IEDM, p.329, 1994 https://doi.org/10.1109/IEDM.1994.383401
  9. Y. Tamura, S. Ohkubo, T. Nakanish, Y. Kataoka, K. Irino and K. Takasaki, 'Suppression of Hot Carrier Degradation in LCD n-MOSFETs with Gate $N_2O$-Nitrided O3-Oxide,' SSDM, p.536, 1996
  10. R. I. Heged, B. Maiti and P. J. Tobin 'Growth and Film Characteristics of $N_2O$ and NO Oxynitride Gate and Tunnel Dielectrics, 'J. Electrochem. Soc., 144, p.1081, 1997 https://doi.org/10.1149/1.1837535
  11. R. I. Hegde, P. J. Tobin, K. G. Reid, B. Maiti and S. A. Ajuria, 'Growth and surface chemistry of oxynitride gate dielectric using nitric oxide,' Appl. Phys. Lett. 66 (21), p. 2282, 1995 https://doi.org/10.1063/1.113461
  12. I. H. Nam, S. I. Hong, J. S. Sim, B. G. Park and J. D. Lee, 'Ultra-Thin Gate Oxide Grown on Nitrogen Implanted Silicon,' The 6th KCS, p.248, 1999
  13. C. Lin, A. I. Chou, P. Choudhury, J. C. Lee. K. Kumar, B. Doyle and H. R. Soleimani, 'Realability of gate oxide grown on nitrogen implanted Si substrates,' Appl. Phys. Lett. 69, p.3701, 1996 https://doi.org/10.1063/1.117194
  14. H. R. Soleimani, B. S. Doyle and Philipossian, 'Formation of Ultrathin Nitrided $SiO_2$ Oxideds by Direct Nitrogen Implantation into Silicon,' J. Electrochem. Soc., 142, p.L132, 1995
  15. C. T. Liu, Y. Ma. J. Becerro, S. Nakahara, D. J. Eaglesham and S. J. hillenius, 'Preventing boron pentration through 2.5nm gate oxides with nitrogen implant in the Si substrates,' IEEE Electron Device Letters 18, p.105, 1997 https://doi.org/10.1109/55.568768
  16. S. H. Lee, B. J. Cho, J. C. Kim and S. H. Choi, 'Quasi-breakdown of ultrathin gate oxide under high field stress,' IEDM, p.605, 1994 https://doi.org/10.1109/IEDM.1994.383337
  17. M. Depas, T. Nigam and M. M. Heyns, 'Soft Breakdown of Ultra-Thin Gate Oxide Layers,' IEEE Trans. On Electron Devices 43, p. 1499 , 1996 https://doi.org/10.1109/16.535341