• ETRI Journal
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• v.37 no.1
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• pp.147-156
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• 2015

A typical solid-state drive contains several independent channels that can be operated in parallel. To exploit this channel-level parallelism, a variety of works proposed to split consecutive write sequences into small segments and schedule them to different channels. This scheme exploits the parallelism but breaks the spatial locality of write traffic; thus, it is able to significantly degrade the efficiency of garbage collection. This paper proposes a channel-aware write reordering (CAWR) mechanism to schedule write requests to different channels more intelligently. The novel mechanism encapsulates correlated pages into a cluster beforehand. All pages belonging to a cluster are scheduled to the same channels to exploit spatial locality, while different clusters are scheduled to different channels to exploit the parallelism. As CAWR covers both garbage collection and I/O performance, it outperforms existing schemes significantly. Trace-driven simulation results demonstrate that the CAWR mechanism reduces the average response time by 26% on average and decreases the valid page copies by 10% on average, while achieving a similar hit ratio to that of existing mechanisms.

• Proceedings of the KIEE Conference
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• 2006.10c
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• pp.446-448
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• 2006

DRAM with ECC is used widely and the size of DRAW increases. According to this, DRAM initial time, especially the time to make the whole area typical value, 0, increases. This paper introduces the method that without any additional hardware, using characteristic of DRAM and DRAM controller, minimize that memory initial time. Conservative reordering - it eliminates DRAM read time and makes write buffer used - reduces initial time to make the whole DRAM area 0, by 95.36% for DDR DRAM. 9341% for Rambus DRAM.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.2
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• pp.386-392
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• 2015

Data in a image compression codec are processed with a specific regular block size. The processing order of block sized data is changed in specific function blocks and the data is packed in memory and read by a new sequence. To maintain a regular throughput rate, double buffering is normally used that interleaving two block sized memory to do concurrent read and write operations. Single buffering using only one block sized memory can be adopted to the simple data reordering, but when a complicate reordering occurs, irregular address changes prohibit from implementing adequate address generating for single buffering. This paper shows that there is a predictable and recurring regularity of changing address access orders within a finite updating counts and suggests an effective method to implement. The data reordering function using suggested idea is designed with HDL and implemented with TSMC 0.18 CMOS process library. In various scan blocks, it shows more than 40% size reduction compared with a conventional method.