• The Journal of the Korea Contents Association
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• v.15 no.7
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• pp.674-683
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• 2015

One of the issues with the textbooks pertinent to the current study is whether or not the Universal Design for Learning (UDL) factors have been dealt to satisfy students with different aptitudes in learning the core objectives of the lessons. This study develops a modified version of the UDL analysis criteria from the cross curricular criteria to language teaching and learning and uses it to analyze the sequence of digital English textbooks to investigate the descriptive statistics of the UDL factors in the new textbooks. The result shows that the textbook is designed most favorably to the students with the talent of linguistic aptitude and less favorably to the students with other types of aptitudes. The sequence analysis shows that sentence/word length and appearance of new words are incrementally sequenced as students advance upper grades. However, the syntactic complexity of middle school curves up steeply which is different from the elementary school textbooks. The UDL analysis will provide learning factors to consider when designing digital English textbooks to cover different aptitudinal groups.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.2
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• pp.397-404
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• 2013

This paper propose the hardware architecture of face detection hardware system using the AdaBoost algorithm. The proposed structure of face detection hardware system is possible to work in 30frame per second and in real time. And the AdaBoost algorithm is adopted to learn and generate the characteristics of the face data by Matlab, and finally detected the face using this data. This paper describes the face detection hardware structure composed of image scaler, integral image extraction, face comparing, memory interface, data grouper and detected result display. The proposed circuit is so designed to process one point in one cycle that the prosed design can process full HD($1920{\times}1080$) image at 70MHz, which is approximate $2316087{\times}30$ cycle. Furthermore, This paper use the reducing the word length by Overflow to reduce memory size. and the proposed structure for face detection has been designed using Verilog HDL and modified in Mentor Graphics Modelsim. The proposed structure has been work on 45MHz operating frequency and use 74,757 LUT in FPGA Xilinx Virtex-5 XC5LX330.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2007.06a
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• pp.778-781
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• 2007

RSA crypto-processors equipped with more than 1024 bits of key space handle the entire key stream in units of blocks. The RSA processor which will be the target design in this paper defines the length of the basic word as 128 bits, and uses an 256-bits register as the accumulator. For efficient execution of 128-bit multiplication, 32b*32b multiplier was designed and adopted and the results are stored in 8 separate 128-bit registers according to the status flag. In this paper, an efficient method to execute 128-bit MAC (multiplication and accumulation) operation is proposed. The suggested method pre-analyze the all possible cases so that the MAC unit can remove unnecessary calculations to speed up the execution. The proposed architecture protype of the MAC unit was automatically synthesized, and successfully operated at 20MHz, which will be the operation frequency in the target RSA processor.

• Journal of IKEEE
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• v.8 no.1 s.14
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• pp.128-135
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• 2004

This paper proposes a phase measurement algorithm which is based on the recursive implementation of sliding-DFT. The algorithm is designed to have a robust behavior against the erroneous factors of frequency drift, additive noise, and twiddle factor approximation. The size of phase error caused by the finite wordlength implementation of DFT twiddle factors is shown significantly lower than that of magnitude error. The drastic reduction of the phase error is achieved by the exploitation of the quadruplet symmetry characteristics of the approximated twiddle factors in the complex plane. Four channel power-line phase measurement system is also designed and implemented based on the time-multiplexed sharing architecture of the proposed algorithm. The operation of the developed system is also verified by the experiment performed under the test environment implemented with the multi-channel function generator and the on-line interfaced host processor system. The proposed algorithm's features of phase measurement accuracy and its robustness against the finite wordlength effects can provide a significant impact especially for the ASIC or microprocessor based embedded system applications where the enhanced processing speed and implementation simplicity are crucial design considerations.

• Journal of the Korean Institute of Intelligent Systems
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• v.13 no.1
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• pp.1-5
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• 2003

In this paper, we realized a system that converts the character images of the printed Korean alphabet (Hangul) to the editable text documents by using the black and white CCD camera, We were able to abstract the contours information of the character which is based on the structural character by using the boundary tracing technique that is strong to the noise on the character recognition. By using the contours information, we recognized the horizontal vowels and vertical vowels of the character image and classify the character into the six patterns. After that, the character is divided to the unit of the consonant and vowel. The vowels are recognized by using the maximum length projection. The separated consonants are recognized by comparing the inputted pattern with the standard pattern that has the phase information of the boundary line change. We realized a system that the recognized characters are inputted to the word editor with the editable KS Hangul completion type code.

• The Journal of the Acoustical Society of Korea
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• v.22 no.4
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• pp.299-307
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• 2003

There have been many studies on speaker normalization which aims to minimize the effects of speaker's vocal tract length on the recognition performance of the speaker independent speech recognition system. In this paper, we propose a simple vector quantizer based linear warping speaker normalization method based on the observation that the vector quantizer can be successfully used for speaker verification. For this purpose, we firstly generate an optimal codebook which will be used as the basis of the speaker normalization, and then the warping factor of the unknown speaker will be extracted by comparing the feature vectors and the codebook. Finally, the extracted warping factor is used to linearly warp the Mel scale filter bank adopted in the course of MFCC calculation. To test the performance of the proposed method, a series of recognition experiments are conducted on discrete HMM with thirteen mono-syllabic Korean number utterances. The results showed that about 29% of word error rate can be reduced, and that the proposed warping factor extraction method is useful due to its simplicity compared to other line search warping methods.

• Journal of the Institute of Electronics Engineers of Korea TE
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• v.37 no.5
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• pp.7-16
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• 2000

This paper described a design and implementation of the division/square-root for a redundant floating point binary number using high-speed quotient selector. This division/square-root used the method of a redundant binary addition with 25MHz clock speed. The addition of two numbers can be performed in a constant time independent of the word length since carry propagation can be eliminated. We have developed a 16-bit VLSI circuit for division and square-root operations used extensively in each iterative step. It performed the division and square-toot by a redundant binary addition to the shifted binary number every 16 cycles. Also the circuit uses the nonrestoring method to obtain a quotient. The quotient selection logic used a leading three digits of partial remainders in order to be implemented in a simple circuit. As a result, the performance of the proposed scheme is further enhanced in the speed of operation process by applying new quotient selection addition logic which can be parallelly process the quotient decision field. It showed the speed-up of 13% faster than previously presented schemes used the same algorithms.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.1
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• pp.34-40
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• 1999

Reed-Solomon(RS) codes have been employed to correct burst errors in applications such as CD-ROM, HDTV, ATM and digital VCRs. For the decoding RS codes, the Berlekamp-Massey algorithm, Euclidean algorithm and modified Euclidean algorithm(MEA) have been developed among which the MEA becomes the most popular decoding scheme. We propose an efficient recursive cell architecture suitable for the MEA. The advantages of the proposed scheme are twofold. First, The proposed architecture uses about 25% less clock cycles required in the MEA operation than[1]. Second, the number of recursive MEA cells can be reduced, when the number of clock cycles spent in the MEA operation is larger than code word length n. thereby buffer requirement for the received words can be reduced. For demonstration, the MEA circurity for (128,124) RS code have been described and the MEA operation is verified through VHDL.

• Journal of the East Asian Society of Dietary Life
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• v.3 no.1
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• pp.12-17
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• 1993

This book is named 'The Ryuk-Jab-Rok' because it was written in the last page of 1820's almanac. This book is written purely in Korean and has not been published yet. This book comprises twenty eight items, among which there are eight items of vegetable preserving method, ten items of Jook preparation methods(a kind of cereal soup), nine items of Pyun-Myun methods(a kind of rice cakes and noodles) and Yak-Bab(a kind of spiced rice). In vegetable preserving method, the eggplant, the cucumber and a songi mushroom were preserved with the drying method., A radish, a sorojangii, and the root of white cabbage were used with the cold temperature preservation. A garlic was dried after salting. The sprouts of DooRub, which were coming in the hot room, were used. In the Jook preparations, there were five animal materials which were lamb, chick, crudian, oyster and abalone. In nine Pyun-Myun methods, Jap-Gua-Sil was illegible because the letters were not clear. Among eight items, the stick rice was used in four cases, the regular rice in two cases. The ground pine nuts, honey and the Chinese date were used most ofter. And the sesame salt and the chestnut were next. The analysis of the terms I this book revealed that 26 items were used for cooking processes. And it also showed us that there were seven kind of cutting procedure and eight kinds of heating procedure. The shapes and size of foods were revealed at only three places in all items. The one-chi(chi ; abut three cm) and three-Ja(Ja ; about thirty cm) which the terms represent the length were revealed twice and once respectively in this book. In the taste description, 'the good', the most common word, was used in seven times, and which was the most frequently introduce case. The measuring unit is hard to revive since the measurements were taken by the container, which were Jong-Ja, Sabal and Tang-gii, then in use. Fifteen kinds of containers and cookers were used for preparing foods. And all of them are now I use.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.9 no.6
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• pp.1195-1201
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• 2005

This paper deals with procedures and results for teal time implementation of G.729 speech coder and channel coder including convolution codec, viterbi decoder, and interleaver using a fixed point DSP chip for radio communication systems. We described the method for real-time implementation based on integer simulation results and explained the implemented results by quality performance and required complexity for real-time operation. The required complexity was 24MIPS and 9MIPS in computational load, and 12K words and 4K words in execution code length for speech and channel. The functional evaluation was performed into two steps. The one was bit exact comparison with a fixed point C code, the other was executed by actual speech samples and error test vectors. Unlik other results such as individual implementation, We implemented speech and channel coders on a DSP chip with 160MIPS computation capability and 64 K words memory on chip. This results outweigh the conventional methods in the point of system complexity and implementation cost for radio communication system.