• Title/Summary/Keyword: wireless hardware

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A Design of RS Decoder for MB-OFDM UWB (MB-OFDM UWB 를 위한 RS 복호기 설계)

  • Choi, Sung-Woo;Shin, Cheol-Ho;Choi, Sang-Sung
    • Proceedings of the Korea Electromagnetic Engineering Society Conference
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    • 2005.11a
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    • pp.131-136
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    • 2005
  • UWB is the most spotlighted wireless technology that transmits data at very high rates using low power over a wide spectrum of frequency band. UWB technology makes it possible to transmit data at rate over 100Mbps within 10 meters. To preserve important header information, MB-OFDM UWB adopts Reed-Solomon(23,17) code. In receiver, RS decoder needs high speed and low latency using efficient hardware. In this paper, we suggest the architecture of RS decoder for MB-OFDM UWB. We adopts Modified-Euclidean algorithm for key equation solver block which is most complex in area. We suggest pipelined processing cell for this block and show the detailed architecture of syndrome, Chien search and Forney algorithm block. At last, we show the hardware implementation results of RS decoder for ASIC implementation.

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Architecture of RS decoder for MB-OFDM UWB

  • Choi, Sung-Woo;Choi, Sang-Sung;Lee, Han-Ho
    • Proceedings of the Korea Society of Information Technology Applications Conference
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    • 2005.11a
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    • pp.195-198
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    • 2005
  • UWB is the most spotlighted wireless technology that transmits data at very high rates using low power over a wide spectrum of frequency band. UWB technology makes it possible to transmit data at rate over 100Mbps within 10 meters. To preserve important header information, MBOFDM UWB adopts Reed-Solomon(23,17) code. In receiver, RS decoder needs high speed and low latency using efficient hardware. In this paper, we suggest the architecture of RS decoder for MBOFDM UWB. We adopts Modified-Euclidean algorithm for key equation solver block which is most complex in area. We suggest pipelined processing cell for this block and show the detailed architecture of syndrome, Chien search and Forney algorithm block. At last, we show the hardware implementation results of RS decoder for ASIC implementation.

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Development of a smart wireless sensing unit using off-the-shelf FPGA hardware and programming products

  • Kapoor, Chetan;Graves-Abe, Troy L.;Pei, Jin-Song
    • Smart Structures and Systems
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    • v.3 no.1
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    • pp.69-88
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    • 2007
  • In this study, Field-Programmable Gate Arrays (FPGAs) are investigated as a practical solution to the challenge of designing an optimal platform for implementing algorithms in a wireless sensing unit for structuralhealth monitoring. Inherent advantages, such as tremendous processing power, coupled with reconfigurable and flexible architecture render FPGAs a prime candidate for the processing core in an optimal wireless sensor unit, especially when handling Digital Signal Processing (DSP) and system identification algorithms. This paper presents an effort to create a proof-of-concept unit, wherein an off-the-shelf FPGA development board, available at a price comparable to a microprocessor development board, was adopted. Data processing functions, including windowing, Fast Fourier Transform (FFT), and peak detection, were implemented in the FPGA using a Matlab Simulink-based high-level abstraction tool rather than hardware descriptive language. Simulations and laboratory tests were carried out to validate the design.

Design and Implementation of the subscriber MAC protocol in the BWA system

  • Hwang, You-Sun;Kim, Eung-bae
    • Proceedings of the IEEK Conference
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    • 2003.07a
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    • pp.569-572
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    • 2003
  • The broadband wireless access industry, which provides high-tate network connections to stationary sites, has matured to the point at which it now has a standard for second-generation wireless metropolitan area networks. IEEE Standard 802.16, with its WirelessMAN air interface, set the stage for widespread and effective deployments worldwide. This paper presents an implementation of media access control that can be applied to BWA (Broadband Wireless Access) system. Medium access control (MAC) is a key issue in multi-access networks where a common channel is shared by many users. The designed MAC prototype roughly consists of MAC Hardware and MAC Software. The MAC Hardware part includes timing process, MAC transmission control, MAC reception control, and CRC/HCS process. The MAC Software part includes control of MAC signaling, network interface, and Physical (PHY) control. The designed MAC protocol will be integrated with the PHY of BWA in future and we can test overall system performance of MAC and PHY.

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A Study on Hardware Design Technique of Wireless LAN Using Spread Spectrum (SS를 이용한 무선 LAN의 하드웨어 설계기술)

  • 최희주;박지언;박재운
    • Journal of the Korea Society of Computer and Information
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    • v.1 no.1
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    • pp.37-52
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    • 1996
  • In this paper. we aim at accomplishment of wireless LAN system providing more advanced skills and services by realizing frequency band spread LAN that Is one of the systems on the basis of present IEEE 802.11 standard system. Including BPF. we realized hardware of wireless LAN and CSMA software program. Using this system, we can establish the PC wireless LAN.

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Wireless Lan System And Its Applying to the Environment Noise Mapping (무선 인터넷 시스템을 이용한 소음 오염도 측정)

  • 김흥섭;이상권
    • Proceedings of the Korean Society for Noise and Vibration Engineering Conference
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    • 2002.05a
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    • pp.286-289
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    • 2002
  • This paper proposes wireless fan system as noise measurement system. It is easy to combine measurement system(Hardware) and analytic system(software) to the Wireless tan system. Thus wireless fan system can be applied to noise mapping system and noise monitoring system. This paper show noise measurement experiment and result using wireless lan system.

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A Fast stream cipher Canon (고속 스트림 암호 Canon)

  • Kim, Gil-Ho
    • Journal of Korea Society of Industrial Information Systems
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    • v.17 no.7
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    • pp.71-79
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    • 2012
  • Propose stream cipher Canon that need in Wireless sensor network construction that can secure confidentiality and integrity. Create Canon 128 bits streams key by 128 bits secret key and 128 bits IV, and makes 128 bits cipher text through whitening processing with produced streams key and 128 bits plaintext together. Canon for easy hardware implementation and software running fast algorithm consists only of simple logic operations. In particular, because it does not use S-boxes for non-linear operations, hardware implementation is very easy. Proposed stream cipher Canon shows fast speed test results performed better than AES, Salsa20, and gate number is small than Trivium. Canon purpose of the physical environment is very limited applications, mobile phones, wireless Internet environment, DRM (Digital Right Management), wireless sensor networks, RFID, and use software and hardware implementation easy 128 bits stream ciphers.

Hardware Implementation of Radio Port Controller System for Wireless Local Loop Radio Network (무선 가입자망의 기지국 제어기 시스템 하드웨어 구현)

  • Koo, Je-Gil
    • Journal of the Institute of Electronics Engineers of Korea TE
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    • v.37 no.1
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    • pp.50-57
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    • 2000
  • By supporting wireless communication technology, there is gradually expansion of the commercial application for Wireless Local Loop(WLL) technology, which is to replace existing telephone line with wireless one. The WLL system application helps a operator to have merits of the installation and maintenance of line and also a subscriber to make a high speed value-added service. As mentioned above reasons for both sides, many manufactories and operators are concerned with development and application respectively. This paper presents hardware implementation of Radio Port Controller(RPC) and also describes the system configuration, functions, and Inter Processor Communication(IPC) structure of RPC. We performed inter-module communication test via IPC backplane bus. And inter-module integration test also completed through data communication and signal waveform measurement repeatedly.

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Rapid Implementation of the MAC and Interface Circuits fot the Wireless LAN Cards Using FPGA

  • Jiang, Songchar
    • Journal of Communications and Networks
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    • v.1 no.3
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    • pp.201-212
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    • 1999
  • This paper studies the rapid design and implementation of the medium access control(MAC) and related interface circuits for 802.11 wireless LANs based on the field programmed gate ar-ray(FPGA) technology. Our design is thus aimed to support both the distributed coordination function (DCF) and the point coordination function(PCF) with the aid of FPGA technology. Further-more, in an infrastructure network, some stations may serve as the access points (APs) which may function like a learning bridge. This paper will also discuss how to design for such application. The hardware of the MAC and interface may at least consist of three major parts: wireless transmission and reception processes and in-terface, host(bus) interface, and the interface to the distributed system (optional). Through the increasing popularity of FPGA de-sign, this paper presents how Complex Programmable Logic De-vices(CPLD) can be utilized for speedy design of prototypes. It also demonstrates that there is much room for low-cost hardware prototype design to accelerate the processing speed of the MAC control function and for field testing.

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HW/SW Co-Design of an Adaptive Frequency Decision in the Bluetooth Wireless Network

  • Moon, Sang-Ook
    • Journal of information and communication convergence engineering
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    • v.7 no.3
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    • pp.399-403
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    • 2009
  • In IEEE 802.15.1 (Bluetooth) Ad-hoc networks, the frequency is resolved by the specific part of the digits of the Device clock and the Bluetooth address of the Master device in a given piconet. The piconet performs a fast frequency hopping scheme over 79 carriers of 1-MHz bandwidth. Since there is no coordination between different piconets, packet collisions may occur if two piconets are located near one another. In this paper, we proposed a software/hardware co-design of an adaptive frequency decision mechanism so that more than two different kinds of wireless devices can stay connected without frequency collision. Suggested method was implemented with C program and HDL (Hardware Description Language) and automatically synthesized and laid out. The adaptive frequency hopping circuit was implemented in a prototype and showed its operation at 24MHz correctly.