• 한국전기전자재료학회논문지
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• 제16권12S호
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• pp.1237-1241
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• 2003

In this paper, we report a novel RF-MEMS packaging technology with lightweight, small size, and short electric path length. To achieve this goal, we used the ultra thin silicon substrate as a packaging substrate. The via holes lot vortical feed-through were fabricated on the thin silicon wafer by wet chemical processing. Then, via holes were filled and micro-bumps were fabricated by electroplating. The packaged RF device has a reflection loss under 22 〔㏈〕 and a insertion loss of -0.04∼-0.08 〔㏈〕. These measurements show that we could package the RF device without loss and interference by using the vertical feed-through. Specially, with the ultra thin silicon wafer we can realize of a device package that has low-cost, lightweight and small size. Also, we can extend a 3-D packaging structure by stacking assembled thin packages.

• 센서학회지
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• 제15권1호
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• pp.58-64
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• 2006

In this study, we describe a low-temperature wafer-level thermocompression bonding using electroplated gold seal line and bonding pads by electroplating method for RF-MEMS devices. Silicon wafers, electroplated with gold (Au), were completely bonded at $320^{\circ}C$ for 30 min at a pressure of 2.5 MPa. The through-hole interconnection between the packaged devices and external terminal did not need metal filling process and was made by gold films deposited on the sidewall of the throughhole. This process was low-cost and short in duration. Helium leak rate, which is measured to evaluate the reliability of bonded wafers, was $2.7{\pm}0.614{\times}10^{-10}Pam^{3}/s$. The insertion loss of the CPW packaged was $-0.069{\sim}-0.085\;dB$. The difference of the insertion loss between the unpackaged and packaged CPW was less than -0.03. These values show very good RF characteristics of the packaging. Therefore, gold thermocompression bonding can be applied to high quality hermetic wafer level packaging of RF-MEMS devices.

• 한국전자파학회지:전자파기술
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• 제24권2호
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• pp.23-34
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• 2013

Over the past several decades in the microelectronics industry, devices have gotten smaller, thinner, and lighter, without any accompanying degradation in quality, performance, and reliability. One permanent and deniable trend in packaging as well as wafer fabrication industry is system integration. The proliferating options for system integration, recently, are driving change across the overall semiconductor industry, requiring more investment in developing, ramping and supporting new die-, wafer- and board-level solution. The trend toward 3D system integration and miniaturization in a small form factor has accelerated even more with the introduction of smartphones and tablets. In this paper, the key issues and state of the art for system integration in the packaging process are introduced, especially, focusing on ease transition to next generation packaging technologies like through silicon via (TSV), 3D wafer-level fan-out (WLFO), and chip-on-chip interconnection. In addition, effective solutions like fine pitch copper pillar and MEMS packaing of both advanced and legacy products are described with several examples.

• 한국재료학회:학술대회논문집
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• 한국재료학회 2007년도 춘계학술발표대회 및 제12회 신소재 심포지엄
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• pp.14.2-14.2
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• 2007

• 한국마이크로전자및패키징학회:학술대회논문집
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• 한국마이크로전자및패키징학회 2006년도 SMT/PCB 기술세미나
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• pp.87-117
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• 2006

• 한국마이크로전자및패키징학회:학술대회논문집
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• 한국마이크로전자및패키징학회 1999년도 1st Korea-Japan Advanced Semiconductor Packaging Technology Seminar
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• pp.87-126
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• 1999

• 한국마이크로전자및패키징학회:학술대회논문집
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• 한국마이크로전자및패키징학회 2003년도 International Symposium
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• pp.103-107
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• 2003

• 한국마이크로전자및패키징학회:학술대회논문집
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• 한국마이크로전자및패키징학회 2001년도 추계 기술심포지움
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• pp.119-123
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• 2001

In this paper, a new structure and fabrication method for the wafer level package(WLP) is presented. A packaged VLSI chip is encapsulated by a parylene(which is a low k material) layer as a dielectric layer and is molded by SUB photo-epoxy with dielectric constant of 3.0 at 100 MHz. The electrical parameters (R, L, C) of package traces are extracted by using the Maxwell 3-D simulator. Based on HSPICE simulation results, the proposed wafer level package can operate for frequencies up to 20GHz.

• 대한기계학회논문집A
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• 제25권1호
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• pp.11-15
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• 2001

We present the design and strength evaluation of an anodically bonded pressurized cavity array, based on the energy release rate measured from the anodically bonded plates of two dissimilar materials. From a theoretical analysis, a simple fracture mechanics model of the pressurized cavity array has been developed. The energy release rate (ERR) of the bonded cavity with an infinite bonding length has been derived in terms of cavity pressure, cavity size, bonding length, plate size and material properties. The ERR with a finite bonding length has been evaluated from the finite element analysis performed for varying cavity and plate sizes. It is found that, for an inter-cavity bonding length greater than the half of the cavity length, the bonding strength of cavity array approaches to that of the infinite plate. For a shorter bonding length, however, the bonding strength of the cavity array is monotonically decreased with the ratio of the bonding length to the cavity length. The critical ERR of 6.21J/㎡ has been measured from anodically bonded silicon-glass plates. A set of critical pressure curves has been generated for varying cavity array sizes, and a design method of the pressurized cavity array has been developed for the failure-free wafer-level packaging of MEMS devices.

• 한국마이크로전자및패키징학회:학술대회논문집
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• 한국마이크로전자및패키징학회 2000년도 The IMAPS-Korea Workshop 2000 Emerging Technology on Packaging
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• pp.55-85
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• 2000

MEMS(Micro Electro Mechanical System) technology. MEMS Inertial Sensors promise a new wide market for many areas -Challenge. significant cost reduction by wafer level packaging and testing. decreasing of power consumption by miniaturization. enhancing of performance and reliability. on-chip integration for multiplicity. MEMS is newly emerging technology.