• Proceedings of the Korean Society of Precision Engineering Conference
• /
• 2006.05a
• /
• pp.533-534
• /
• 2006

Micro pyramid pattern and its array are designed to enhance the brightness and its uniformity of LGP which is one of key parts in LCD. The designed micro pyramid patterns are fabricated on a Si-wafer first through MEMS process and then a Ni-stamper is electro-plated from the Si pattern master. Adopting the fabricated Ni-stamper, LGPs are injection molded at different mold temperatures and the fidelity of the pattern replication is estimated for each molding conditions and pattern locations. The replicated patterns are found to have some defect such as local short shot or micro weld line which are believed to have negative effect on the performance of the LGP.

• Tribology and Lubricants
• /
• v.39 no.1
• /
• pp.28-34
• /
• 2023

Because of their cleanliness, low friction, and high stiffness, aerostatic bearings are used in numerous applications. Aerostic bearings that use porous materials as means of flow restriction have higher stiffness than other types of bearings and have been successfully applied as guide bearings, which have high motion accuracy requirements. However, the performances of porous bearings exhibit strong nonlinearity and can vary considerably depending on design parameters. Therefore, accurate prediction of the performance characteristics of porous bearings is necessary or their successful application. This study presents a porous bearing design and performance analysis for a spindle used in wafer polishing. The Reynolds and Darcy flow equations are solved to calculate the pressures in the lubrication film and porous busing, respectively. To verify the validity of the proposed analytical model, the calculated pressure distribution in the designed bearing is compared with that derived from previous research. Additional parametric studies are performed to determine the optimal design parameters. Analytical results show that optimal design parameters that obtain the maximum stiffness can be derived. In addition, the results show that cross-coupled stiffness increases with rotating speed. Thus, issues related to stability should be investigated at the design stage.

• 한국신재생에너지학회:학술대회논문집
• /
• 2010.06a
• /
• pp.72.1-72.1
• /
• 2010

Thin film a-Si solar cells deposited by PECVD have many advantages compared to the traditional crystalline Si solar cells. They do not require expensive Si wafer, the process temperature is relatively low, possibility of scaling up for mass production, etc. In order to produce thin film solar cells, understanding the relationship between the material characteristics and deposition conditions is important. It has been reported by many groups that the band gap of the a-Si material and the deposition rate has an linear relationship, when RF power is used to control both. However, when the process pressure is changed in order to control the deposition rate and the band gap, a diversion from the well known linear relationship occurs. Here, we explain this diversion by the deposition condition crossing different plasma regions in the Paschen curve with a simple model. This model will become a guide to which condition a-Si thin films must be fabricated in order to get a high quality film.

• Journal of the Korean Vacuum Society
• /
• v.19 no.3
• /
• pp.230-235
• /
• 2010

In this paper, we controlled the deposition rate and reflective index with process conditions that are TCP power, gas flow ratio and bias for optical properties of $SiO_2$ thin film using TCP-CVD equipment. We obtained a excellent $SiO_2$ thin film which has a excellent uniformity (<1 [%]), deposition rate (0.28 [${\mu}m$/ min]) and reflective index (1.4610-1.4621) within 4" wafer with process conditions ($SiH_4:O_2$=50 : 100 [sccm], TCP power 1 [kW], bias 200 [W]) at [$300^{\circ}C$].

• Journal of the Korean Society for Precision Engineering
• /
• v.22 no.12 s.177
• /
• pp.51-60
• /
• 2005

This paper describes a robust control scheme for high-speed and long stroke scanning motion of high precision linear motor system consisting of linear motor, air bearing guide and position measurement system using heterodyne interferometer. Nowadays, semiconductor process and inspection of wafer or LCD need high speed and long travel length for their high throughput and extremely small velocity fluctuations or tracking errors. In order to satisfy these conditions, linear motor system are widely used because they have large thrust force and do not need motion conversion mechanisms such as ball screw, rack & pinion or capstan with which the system are burdened. However linear motors have a problem called force ripple. Force ripple deteriorates the tracking performances and makes periodic position errors. So, force ripple must be compensated. To maximize the tracking performance of linear motor system, we propose the control scheme which is composed of a robust control method, Time Delay Controller (TDC) and a feedforward control method, Zero Phase Error Tracking Control (ZPETC) for accurate tracking a given trajectory and an adaptive force ripple compensation (AFC) algorithm fur estimating and compensating force ripple. The adaptive ripple compensation is continuously refined on the basis of tracking error. Computer simulation results based on modeled parameters verify the effectiveness of the proposed control scheme for high-speed, long stroke and high precision scanning motion and show that the proposed control scheme can achieve a sup error tracking performance in comparison to conventional TDC control.

• Journal of the Semiconductor & Display Technology
• /
• v.17 no.4
• /
• pp.42-45
• /
• 2018

As The semiconductor decrease from 10 nanometer to 7 nanometer, It is suggested that "More than Moore" is needed to follow Moore's Law, which has been a guide for the semiconductor industry. Fan-Out Wafer Level Package(FOWLP) is considered as the key to "More than Moore" to lead the next generation in semiconductors, and the reasons are as follows. the fan-out WLP does not require a substrate, unlike conventional wire bonding and flip-chip bonding packages. As a result, the thickness of the package reduces, and the interconnection becomes shorter. It is easy to increase the number of I / Os and apply it to the multi-layered 3D package. However, FOWLP has many issues that need to be resolved in order for mass production to become feasible. One of the most critical problem is the warpage problem in a process. Due to the nature of the FOWLP structure, the RDL is wired to multiple layers. The warpage problem arises when a new RDL layer is created. It occurs because the solder ball reflow process is exposed to high temperatures for long periods of time, which may cause cracks inside the package. For this reason, we have studied warpage in the FOWLP structure using commercial simulation software through the implementation of the reflow process. Simulation was performed to reproduce the experiment of products of molding compound company. Young's modulus and poisson's ratio were found to be influenced by the order of influence of the factors affecting the distortion. We confirmed that the lower young's modulus and poisson's ratio, the lower warpage.