• 한국정보디스플레이학회:학술대회논문집
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• 2006.08a
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• pp.399-402
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• 2006

A new voltage-scaled compensation pixel which employs 3 p-type poly-Si TFTs and 2 capacitors without additional control line has been proposed and verified. The proposed pixel does not employ the $V_{TH}$ memorizing and cancellation, but scales down the inevitable $V_{TH}$ variation of poly-Si TFT. Also the troublesome narrow input range of $V_{DATA}$ is increased and the $V_{DD}$ supply voltage drop is suppressed. In our experimental results, the OLED current error is successfully compensated by easily controlling the proposed voltage scaling effects.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.59 no.10
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• pp.1733-1740
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• 2010

KPX(Korea Power Exchange) predicts that summer peak load will be 70,700MW and system overload will be 150% from contingency analysis. This paper presents a method to operate power system at 2010 summer peak. about equipment variation, power system variation, analysis results of voltage stability, and the method to relief overload by comparing 2009 and 2010. Especially, transmission constraints to prevent global contingency in Korea power system and the role of SPS(Special Protection System) to prevent voltage collapse when fault occurs are introduced.

• Proceedings of the KIEE Conference
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• 1997.07c
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• pp.867-870
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• 1997

This paper presents application of battery energy storage system(BESS) for interconnection with power distribution system. We configured interconnection model using PSCAD/EMTDC program. The simulation for voltage regulation on BESS interconnection with power distribution analyzes transient voltage variation, steady state voltage variation, and voltage of reverse power flow at interconnected feeder and nearby feeder.

• Proceedings of the KIEE Conference
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• 1997.07d
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• pp.1205-1209
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• 1997

When the short fault current is flowed into a fuse, the notch of element is melted, and burnbacked by arc plasma, which caused by the voltage of fuse at both ends. The cutoff ability of fuse is heavily influenced by the degree of burnback. In this paper, we investigated the amount of burnback to the applied voltage di/dt variation, As a result, we confirmed that the amount of burnback is proportional to the variation of the applied voltage.

• ETRI Journal
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• v.36 no.4
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• pp.643-653
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• 2014

To reduce interconnect delay and power consumption while improving chip performance, a three-dimensional integrated circuit (3D IC) has been developed with die-stacking and through-silicon via (TSV) techniques. The power supply problem is one of the essential challenges in 3D IC design because IR-drop caused by insufficient supply voltage in a 3D chip reduces the chip performance. In particular, power bumps and TSVs are placed to minimize IR-drop in a 3D power delivery network. In this paper, we propose a design methodology for 3D power delivery networks to minimize the number of power bumps and TSVs with optimum mesh structure and distribute voltage variation more uniformly by shifting the locations of power bumps and TSVs while satisfying IR-drop constraint. Simulation results show that our method can reduce the voltage variation by 29.7% on average while reducing the number of power bumps and TSVs by 76.2% and 15.4%, respectively.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.12
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• pp.37-42
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• 1997

A new temperature and supply-insensitive CMOS current reference circuit was designed and tested. Te temperature insensuitivity was achieved by eliminating the mobility dependence term through the multiplication of two current components, one which is proportional to mobility and the other which is inversely proportional to mobility, by using a newly designed CMOS square root circuit. The CMOS sqare root circuit was derived from its bipolar counterpart by operating the MOS transistors in the subthreshold region. The supply insensitivity was achieved by using an internal voltage generator. Te test chip was designed ans sent out for fabrication by using a 2.mu.m double-poly double-metal n-well CMOS technology. When an external voltage source was used for the square root circuit, the maximum variation and the average temperature sensitivity were measured to be 3% and 21.4ppm/.deg.C, respectively, for the temperature range of -15~130.deg.C. The maximum current variation with supply voltage was measured to be 3% within the commerical supply voltage range of 4.5~5.5V at 30.deg. C.

• Journal of Information Display
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• v.7 no.3
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• pp.9-12
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• 2006

A new voltage-scaled compensation pixel which employs 3 p-type poly-Si TFTs and 2 capacitors without additional control line has been proposed and verified. The proposed pixel does not employ the $V_{TH}$ memorizing and cancellation, but scales down the inevitable $V_{TH}$ variation of poly-Si TFT. Also the troublesome narrow input range of $V_{DATA}$ is increased and the $V_{DD}$ supply voltage drop is suppressed. In our experimental results, the OLED current error is successfully compensated by easily controlling the proposed voltage scaling effects.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2001.07a
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• pp.772-775
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• 2001

This paper investigated that resonant frequencies of microstrip patch antenna were frequency aigle when PZT were used as the antenna substrates. The resonant frequencies of the antenna using the piezoelectric substrate were able to be controlled by applied voltage. The frequency variation of the air gap antenna was 16MHz when the voltage variation was 12[KV/cm].

• Progress in Superconductivity and Cryogenics
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• v.4 no.1
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• pp.73-77
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• 2002

The variation of critical current by the formation of crack in a high temperature super-conducting tape was studied by experimental and numerical analyses. The current-voltage relation of HTS tape is measured by the four-point measurement method. Numerical analyses are used to solve two dimensional heat conduction equation, considering the temperature distribution. By comparing current-voltage relation of experimental and numerical results, the validity of numerical method is verified.

• Journal of Power Electronics
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• v.7 no.1
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• pp.13-20
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• 2007

LLC resonant converters display many advantages over the conventional LC series resonant converter such as narrow frequency variation over wide range of load and input variation and zero voltage switching even under no load conditions. This paper presents analysis and design consideration for the half bridge LLC resonant converter. Using the fundamental approximation, the gain equation is obtained, where the leakage inductance in the transformer secondary side is also considered. Based on the gain equation, the practical design procedure is investigated to optimize the resonant network for a given input/output specifications. The design procedure is verified through an experimental prototype of the 115W half-bridge LLC resonant converter.