• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.10
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• pp.1744-1750
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• 2008

As the computing and network technique move rm and spread widly, the usage of multimedia application becomes in general while the usage of text based application becomes low. Especially the application which treats the streaming media such as video or movie, one of multimedia data, holds a majority in the usage of computing. MPEG, one of the typical compression standard of streaming media, provides very high compression ratio so that general users could be close to the streaming media with easy usage. However, the encoding of MPEG requires lots of computing power and time. In the paper, we design and implement a parallel MPEG encoder with MPI in cluster envrionment to reduce the encoding time of MPEG.

• IEMEK Journal of Embedded Systems and Applications
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• v.2 no.3
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• pp.129-137
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• 2007

MPEG-4 FGS is one of scalable video coding schemes specified In ISO/IEC 14496-2 Amendment 2, and particularly standardized as a scheme for providing fine granular quality and temporal scalabilities. In this paper, we propose a sign-bit reduction technique in embedded bit-plane coding to enhance the coding efficiency of MPEG-4 FGS system. The general structure of the FGS system for the proposed scheme is based on the standard MPEG-4 FGS system. The proposed FGS enhancement-layer encoder takes as input the difference between the original DCT coefficient and the decision level of the quantizer instead of the difference between the original DCT coefficient and its reconstruction level. By this approach, the sign information of the enhancement-layer DCT coefficients can be the same as that of the base-layer ones at the same frequency index in DCT domain. Thus, overhead bits required for coding a lot of sign information of the enhancement-layer DCT coefficients in embedded bit-plane coding can be removed from the generated bitstream. It is shown by simulations that the proposed FGS coding system provides better coding performance, compared to the MPEG-4 FGS system in terms of compression efficiency.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2009.01a
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• pp.142-147
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• 2009

The recent H.264/AVC video coding standard provides a higher coding efficiency than previous standards. H.264/AVC achieves a bit rate saving of more than 50 % with many new technologies, but it is computationally complex. Most of fast mode decision algorithms have focused on Baseline profile of H.264/AVC. In this paper, a fast block mode decision scheme for P- slices in High profile is proposed to reduce the computational complexity for H.264/AVC because the High profile is useful for broadcasting and storage applications. To reduce the block mode decision complexity in P- pictures of High profile, we use the SAD value after $16{\times}16$ block motion estimation. This SAD value is used for the classification feature to divide all block modes into some proper candidate block modes. The proposed algorithm shows average speed-up factors of 47.42 ${\sim}$ 67.04% for IPPP sequences.

• ETRI Journal
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• v.39 no.5
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• pp.672-682
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• 2017

Video compression exploits statistical, spatial, and temporal redundancy, as well as transform and quantization. In particular, the transform in a frequency domain plays a major role in energy compaction of spatial domain data into frequency domain data. The high efficient video coding standard uses the type-II discrete cosine transform (DCT-II) and type-VII discrete sine transform (DST-VII) to improve the coding efficiency of residual data. However, the DST-VII is applied only to the Intra $4{\times}4$ residual block because it yields relatively small gains in the larger block than in the $4{\times}4$ block. In this study, after rearranging the data of the residual block, we apply the DST-VII to the inter-residual block to achieve coding gain. The rearrangement of the residual block data is similar to the arrangement of the basis vector with a the lowest frequency component of the DST-VII. Experimental results show that the proposed method reduces the luma-chroma (Cb+Cr) BD rates by approximately 0.23% to 0.22%, 0.44% to 0.58%, and 0.46% to 0.65% for the random access, low delay B, and low delay P configurations, respectively.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.11 no.4
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• pp.766-772
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• 2007

H.264/AVC is a new international standard for the compression of video images, in which a deblocking filter has been adopted to remove blocking artifacts. This paper proposes an efficient architecture of deblocking filter in H.264/AVC. By making good use of data dependence between neighboring $4{\times}4$ blocks, the memory size is reduced and the throughput of the deblocking filter processing is increased. Compared to the conventional deblocking filters, the proposed architecture enhances the performance of deblocking filter processing from 1.75 to 4.23 times. Hence the proposed architecture is able to perform real-time deblocking of high-resolution($2048{\times}1024$) video applications.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.9 s.351
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• pp.44-52
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• 2006

Recently developed MPEG-4 Part 2 compression standard provides a novel capability to handle arbitrary video objects. To support this capability, an efficient object segmentation technique is required. This paper proposes a real-time algorithm for foreground object segmentation in video sequences. The proposed algorithm consists of two steps: the first step that segments a video frame into multiple sub-regions using Spatio-Temporal Watershed Transform and the second step in which a foreground object segment is extracted from the sub-regions generated in the first step. For real-time processing, the algorithm is partitioned into hardware and software parts so that computationally expensive parts are off-loaded from a processor and executed by hardware accelerators. Simulation results show that the proposed implementation can handle QCIF-size video at 15 fps and extracts an accurate foreground object.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.43 no.6 s.312
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• pp.97-104
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• 2006

The state-of-the-art H.264/AVC standard was designed for the lossy video coding so that it could not yield the best performance for lossless video coding. In this paper, we propose two efficient intra lossless coding methods by embedding a pixel-wise prediction into the H.264/AVC. One is based on the pixel-wise prediction for the residual signal of the H.264/AVC intra Prediction and the other suggests a newly additional intra prediction mode for the conventional intra prediction. We found that the proposed lossless coding algorithms could achieve approximately $12%{\sim}25%$ more bit saving compared to the H.264/AVC FRExt high profile for several test sequences in terms of a compression ratio.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.3
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• pp.585-593
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• 2017

In this paper, we propose a deblocking filter hardware architecture for low-power HEVC (High-Efficiency Video Coding) in-loop for mobile systems. HEVC performs image compression on a block-by-block basis, resulting in blockage of the image due to quantization error. The deblocking filter is used to remove the blocking phenomenon in the image. Currently, UHD video service is supported in various mobile systems, but power consumption is high. The proposed low-power deblocking filter hardware structure minimizes the power consumption by blocking the clock to the internal module when the filter is not applied. It also has four parallel filter structures for high throughput at low operating frequencies and each filter is implemented in a four-stage pipeline. The proposed deblocking filter hardware structure is designed with Verilog HDL and synthesized using TSMC 65nm CMOS standard cell library, resulting in about 52.13K gates. In addition, real-time processing of 8K@84fps video is possible at 110MHz operating frequency, and operation power is 6.7mW.

• Journal of Korea Multimedia Society
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• v.8 no.8
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• pp.1080-1087
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• 2005

Significant computations for full search (FS) motion estimation have been a big obstacle in real-time video coding and recent MPEG-4 AVC (advanced video coding) standard requires much more computations than conventional MPEG-2 for motion estimation. To reduce an amount of computation of full search (FS) algorithm for fast motion estimation, we propose a new and fast matching algorithm without any degradation of predicted images like the conventional FS. The computational reduction without any degradation in predicted image comes from fast elimination of impossible candidate motion vectors. We obtain faster elimination of inappropriate motion vectors using efficient matching units from localization of complex area in image data and dithering order based matching scan. Our algorithm reduces about $30\%$ of computations for block matching error compared with the conventional partial distortion elimination (PDE) algorithm, and our algorithm will be useful in real-time video coding applications using MPEG-4 AVC or MPEG-2.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2007.10a
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• pp.615-618
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• 2007

It has able to express digital video/audio data from analog and to broadcast it via improvement of video/audio compression technology and publishing standard of MPEG-2 System. Nowaday many System Operators are provide regular digital broadcasting program to customer with their own access program. To provide access program, two process needs that are creating broadcasting information and remultiplexing it with video/audio data, and this solution is providing with high-cost system only. For this reason, digital access program bas week point to product. In this paper, we designed and implemented Generating PSIP Information System to product digital access program which generate PSIP information via receiving broadcasting information from user, and map PSIP information directly to video/audio data.