• The KIPS Transactions:PartB
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• v.12B no.6 s.102
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• pp.637-646
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• 2005

Most of the multimedia contents for DBM services art provided as MPEG-2 bit streams. However, they have to be transcoded to H.264 bit streams for practical services because the standard video codec for DMB is H.264. The existing transcoder architecture is Cascaded Pixel-Domain Transcoding Architecture, which consists of the MPEG-2 dacoding phase and the H.264 encoding phase. This architecture can be easily implemented using MPEG-2 decoder and H.264 encoder without source modifying. However. It has disadvantages in transcoding time and DCT-mismatch problem. In this paper, we propose two kinds of transcoder architecture, DCT-OPEN and DCT-CLOSED, to complement the CPDT architecture. Although DCT-OPEN has lower PSNR than CPDT due to drift problem, it is efficient for real-time transcoding. On the contrary, the DCT-CLOSED architecture has the advantage of PSNR over CPDT at the cost of transcoding time.

• Journal of Broadcast Engineering
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• v.15 no.1
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• pp.52-62
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• 2010

Recently, DVC (Distributed Video Coding) is attracting a lot of research works since this enables us to implement a light-weight video encoder by distributing the high complex tasks such as motion estimation into the decoder side. In order to improve the coding efficiency of the DVC, the existing works have been focused on the efficient generation of side information (SI) or the virtual channel modeling which can describe the statistical channel noise well. But, in order to improve the overall performance, this paper proposes a new scheme that can be implemented with simple bit operations without introducing complex operation. That is, the performance of the proposed scheme is enhanced by using the fact that the Wyner-Ziv (WZ) frame and side information are highly correlated, and by reducing the effect of virtual channel noise which tends to be clustered in some regions. For this aim, this paper proposes an efficient pixel-domain WZ (PDWZ) CODEC which effectively exploits the statistical redundancy by using the code conversion and Gray code, and then reduces the channel noise by using the bit interleaver. Through computer simulations, it is shown that the proposed scheme can improve the performance up to 0.5 dB in objective visual quality.

• Journal of Broadcast Engineering
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• v.26 no.6
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• pp.680-691
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• 2021

Due to the recent developments of attaining 3D contents by using devices such as 3D scanners, the diversity of the contents being used in AR(Augmented Reality)/VR(Virutal Reality) fields is significantly increasing. There are several ways to represent 3D data, and using point clouds is one of them. A point cloud is a cluster of points, having the advantage of being able to attain actual 3D data with high precision. However, in order to express 3D contents, much more data is required compared to that of 2D images. The size of data needed to represent dynamic 3D point cloud objects that consists of multiple frames is especially big, and that is why an efficient compression technology for this kind of data must be developed. In this paper, a motion estimation and compensation method for dynamic point cloud objects using 3D DCT is proposed. This will lead to switching the 3D video frames into I frames and P frames, which ensures higher compression ratio. Then, we confirm the compression efficiency of the proposed technology by comparing it with the anchor technology, an Intra-frame based compression method, and 2D-DCT based V-PCC.

• Journal of Advanced Navigation Technology
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• v.11 no.4
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• pp.485-492
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• 2007

In this paper, we propose the receiver block error detection of the video codec and the image concealment algorithm using fuzzy inference. The proposed error detection and concealment algorithm gets SSD(Summation of Squared Difference) and BMC(Boundary Matching Coefficient) using the temporal and spatial similarity between corresponded blocks in the two successive frames. Proportional constant, ${\alpha}$, for threshold value, TH1 and TH2, is decided after fuzzy data is generated by each parameter. To examine the propriety of the proposed algorithm, random errors are inserted into the QCIF Susie standard image, then the error detection and concealment performance is simulated. To evaluate the efficiency of the algorithm, image quality is evaluated by PSNR for the error detection and concealed image by the existing VLC table and by the proposed method. In the experimental results, the error detection algorithm could detect all of the inserted error, the image quality is improved over 15dB after the error concealment compare to existing error detection algorithm.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.1C
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• pp.72-82
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• 2004

This paper proposes more robust error concealment techniques (ECTs) for MPEG-2 intra coded frame. MPEG-2 source coding algorithm is very sensitive to transmission errors due to the use of variable-length coding. The transmission errors are corrected by error correction scheme, however, they cannot be revised properly. Error concealment (EC) is used to conceal the errors which are not corrected by error correction and to provide minimum visual distortion at the decoder. If errors are generated in intra coded frame, that is the starting frame of GOP, they are propagated to other inter coded frames due to the nature of motion compensated prediction coding. Such propagation of error may cause severe visual distortion. The proposed algorithm in this paper utilizes the spatio-temporal information of neighboring inter coded frames to conceal the successive slices errors occurred in I-frame. The proposed method also overcomes the problems that previous ECTs reside. The proposed algorithm generates consistent performance even in network where the violent transmission errors frequently occur. Algorithm is performed in MPEG-2 video codec and we can confirm that the proposed algorithm provides less visible distortion and higher PSNR than other approaches through simulations.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.47 no.5
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• pp.165-174
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• 2010

The H.264/AVC standard obtained better performance than previous compression standards, but it also increased the computational complexity of CODEC simultaneously. Various techniques recently included at the KTA software developed by VCEG also were increasing its complexity. Especially adaptive interpolation filter has more complexity than two times due to development for coding efficiency. In this paper, we propose low-complexity filter bank to improve speed up of decoding and coding gain. We consists of filter bank of a fixed-simple filter for low-complexity and adaptive interpolation filter for high coding efficiency. Then we compensated using optimal filter at each macroblock-level or frame-level. Experimental results shows a similar coding efficiency compared to existing adaptive interpolation filter and decoding speed of approximately 12% of the entire decoder gained.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.6
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• pp.68-73
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• 2008

In this paper, we propose watermark algorithm called TDWA(Time-Division Watermarking Algorithm) and we applied the proposed algorithm to H.264 video coding standard. We establish that a proposed algorithm is applied to H.264 baseline profile CODEC. The proposed algorithm inserts a watermark into the spatial domain of several frames. We can easily insert strong and invisible watermarks into original pictures using this method. For verification of the proposed algorithm we design hardware core using Verilog-HDL and Excalibur for JM 8.7 code with hardware & software co-simulation. As a result of verification, the PSNR between watermarked pictures and original pictures are more than 60dB and we found the watermark is kept more than 80% after encoding of H.264/AVC with quantization parameter of 28 in baseline profile.

• Journal of IKEEE
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• v.19 no.3
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• pp.342-348
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• 2015

High speed implementation of digital filters is required in high data rate applications such as hard-wired wide band modem and high resolution video codec. Since the critical path of the digital filter is the MAC (multiplication and accumulation) circuit, the filter coefficient with sparse non-zero bits enables high speed implementation with adders of low hardware cost. Compressive sensing has been reported to be very successful in sparse representation and sparse signal recovery. In this paper a filter design method for digital FIR filters with CSD (canonic signed digit) coefficients using compressive sensing technique is proposed. The sparse non-zero signed bits are selected in the greedy fashion while pruning the mistakenly selected digits. A few design examples show that the proposed method can be utilized for designing sparse CSD coefficient digital FIR filters approximating the desired frequency response.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.12
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• pp.167-173
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• 2015

This paper presents a study on the Full-HD HEVC(High Efficiency Video Coding) encoder IP(Intellectual Property) design. The designed IP is for HEVC main profile 4.1, and performs encoding with a speed of 60 fps of full high definition. Before hardware and software design, overall reference model was developed with C language, and we proposed a parallel processing architecture for low-power consumption. And also we coded firmware and driver programs relating IP. The platform for verification of developed IP was developed, and we verified function and performance for various pictures under several encoding conditions by implementing designed IP to FPGA board. Compared to HM-13.0, about 35% decrease in bit-rate under same PSNR was achieved, and about 25% decrease in power consumption under low-power mode was performed.

• Journal of Broadcast Engineering
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• v.16 no.2
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• pp.293-304
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• 2011

In this paper, we proposed a new hardware architecture for motion estimation (ME) which is the most time-consuming unit among H.264 algorithms and designed to the type of intellectual property (IP). The proposed ME hardware consists of buffer, processing unit (PU) array, SAD (sum of absolute difference) selector, and motion vector (MVgenerator). PU array is composed of 16 PUs and each PU consists of 16 processing elements (PUs). The main characteristics of the proposed hardware are that current and reference frames are re-used to reduce the number of access to the external memory and that there is no clock loss during SAD operation. The implemented ME hardware occupies 3% hardware resources of StatixIII EP3SE80F1152C2 which is a FPGA of Altera Inc. and can operate at up to 446.43MHz. Therefore it can process up to 50 frames of 1080p in a second.