• Journal of the Microelectronics and Packaging Society
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• v.14 no.4
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• pp.63-69
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• 2007

We investigated interconnection processes using Cu vias for MEMS sensor packages. Ag paste layer was formed on a glass substrate and used as a seed layer for electrodeposition of Cu vias after bonding a Si substrate with through-via holes. With applying electrodeposition current densities of $20mA/cm^2\;and\;30mA/cm^2$ at direct current mode to the Ag paste seed-layer, Cu vias of $200{\mu}m$ diameter and $350{\mu}m$ depth were formed successfully without electrodeposition defects. Interconnection processes for MEMS sensor packages could be accomplished with Ti/Cu/Ti line formation, Au pad electrodeposition, Sn solder electrodeposition and reflow process on the Si substrate where Cu vias were formed by Cu electrodeposition into through-via holes.

• Korean Journal of Ophthalmology
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• v.32 no.6
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• pp.506-516
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• 2018

Purpose: We measured the thicknesses of the ganglion cell and inner plexiform layer (GCIPL), the macula, and the retinal nerve fiber layer (RNFL) using spectral-domain optical coherence tomography in patients with idiopathic macula holes to analyze the repeatability of these measurements and compare them with those of the fellow eye. Methods: We evaluated 85 patients who visited our retinal clinic. The patients were divided into two groups according to their macular hole size: group A had a size of $<400{\mu}m$, while group B had a size of ${\geq}400{\mu}m$. Repeatability was determined by comparing the thicknesses of the GCIPL, macula, and RNFL with those of the normal fellow eye. Results: The average central macular thickness in patients with macular holes was significantly thicker than that in the normal fellow eye ($343.8{\pm}78.6$ vs. $252.6{\pm}62.3{\mu}m$, p < 0.001). The average thickness of the GCIPL in patients with macular holes was significantly thinner than that in the normal fellow eye ($56.1{\pm}23.4$ vs. $77.1{\pm}12.8{\mu}m$, p < 0.001). There was no significant difference in the average RNFL thickness between eyes with macular holes and fellow eyes ($92.4{\pm}10.0$ vs. $95.5{\pm}10.7{\mu}m$, p = 0.070). There were also no significant differences in the thicknesses of the GCIPL and RNFL among the two groups (p = 0.786 and p = 0.516). The intraclass correlation coefficients for the macula and RNFL were 0.994 and 0.974, respectively, in patients with macular holes, while that for the GCIPL was 0.700. Conclusions: Macular contour change with macular hole results in low repeatability and a tendency of thinner measurement regarding GCIPL thickness determined via spectral-domain optical coherence tomography. The impact of changes in the macular shape caused by macular holes should be taken into consideration when measuring the GCIPL thickness in patients with various eye diseases such as glaucoma and in those with neuro-ophthalmic disorders.

• Korean Membrane Journal
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• v.1 no.1
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• pp.25-37
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• 1999

positron annihilation Lifetime Spectroscopy has been extensively applied in recent years to investigate the free volume in polymers owing to the capability of the electron-positron bound system (positronium) to probe the typical size of sub-nanometric cavities among the macromolecular chains. In this paper we show recent results obtained through this technique in some amorphous polymeric mem-branes(olyurethanes. PUs and polytrimethilsylilpropine PTMSP) after a brief survey of the general features of the annihilation process as well as of the experimental apparatus. Lifetime of o-ps decay({{{{ tau _3}}}}) in PUs increases going from sub {{{{ TAU _g}}}} to over {{{{ TAU _g}}}} temperatures following a sigmoid curve. The coefficient of dilatation of the free volume fraction is shown to be the sum of two contributes due to the variation with T of the number of holes and of their mean volume. PAL spectrum of PTMSP freshly prepared shows four lifetime components: {{{{ tau _3}}}} and {{{{ tau _4}}}}: only are useful for free volume study. Two kinds of holes of different equivalent radius are reported ({{{{ gamma _s}}}} 4.60 nm and {{{{ gamma _1}}}} 0.754) The equivalent volume does not change in a range of 100 K. however the physical aging increases density and decreases oxygen permeability while {{{{ gamma _s}}}} goes down to 0.374 and r1 to 0.735 The number of holes obtained from the intensities{{{{ IOTA _3}}}} and {{{{ IOTA _4}}}} of PAL spectra decreases with aging 21.7% and 3.5% for large and small holes respectively.

• Proceedings of the Korean Society for Technology of Plasticity Conference
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• 2004.11a
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• pp.260-265
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• 2004

LTCC(Low temperature co-fired ceramic) is being recognized as a significant packaging material of electrical devices for the advantages such as relatively low temperature being needed for process, low conductor resistance and high printing resolution. In the process of LTCC electrical devices, the punched via-hole quality is one of the most important factors on the performance of the device. However, its mechanism is very complicated and optimization of the process seems difficult. In this paper, to clarify the process, via-hole punching experiments were carried out and the punched holes were examined in terms of their burr formation. The effects of thickness of PET sheet and ceramic sheet and punch-to-die clearance on via-hole quality were also discussed. Optimum process conditions are proposed and a factor k is introduced to express effect of the process variables.

• Journal of Information Display
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• v.12 no.1
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• pp.47-50
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• 2011

Highly stable amorphous indium.gallium.zinc-oxide (a-IGZO) thin-film transistors (TFTs) were fabricated with an etchstopper and via-hole structure. The TFTs exhibited 40 $cm^2$/V s field-effect mobility and a 0.21 V/dec gate voltage swing. Gate-bias stress induced a negligible threshold voltage shift (${\Delta}V_{th}$) at room temperature. The excellent stability is attribute to the via-hole and etch-stopper structure, in which, the source/drain metal contacts the active a-IGZO layer through two via holes (one on each side), resulting in minimized damage to the a-IGZO layer during the plasma etching of the source/drain metal. The comparison of the effects of the DC and AC stress on the performance of the TFTs at $60^{\circ}C$ showed that there was a smaller ${\Delta}V_{th}$ in the AC stress compared with the DC stress for the same effective stress time, indicating that the trappin of the carriers at the active layer-gate insulator interface was the dominant degradation mechanism.

• Journal of the Semiconductor & Display Technology
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• v.22 no.1
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• pp.94-98
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• 2023

In the case of high-speed data transmission on high multilayer boards, signal coherence is a problem, especially due to the via hole, and a solution to improve return loss or insertion loss by applying a back drill to the via hole is being proposed. In this paper, Near-Field Electromagnetic measurements were made on a high multilayer board to determine how the presence or absence of back drill affects signal consistency. For this purpose, we used a signal generator, spectrum analyzer, and EMC scanner on a test board to determine if it is possible to distinguish between areas with and without back drill in the via holes of the stubs on the board. Also, we analyzed the measured value of S11, S21 and EMC etc. for how much it improves the signal attenuation of the stub with back drill. Through this, we knew that less electromagnetic waves are generated the stub via with back drill. At future research, we will analyze how much it improves the signal loss and electromagnetic waves due to the depth of back drill.

• 한국정보디스플레이학회:학술대회논문집
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• 2008.10a
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• pp.816-819
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• 2008

A negative photoresist formulation was developed utilizing synthesized UV monomers containing imide linkage, photoinitiator, UV oligomer, and alkali developable polymer matrix. It was found that via-holes with good resolution, high transmittance and thermal resistance could be obtained by photolithographic process utilizing the negative-type photoresist formulations.

• Journal of the Microelectronics and Packaging Society
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• v.22 no.4
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• pp.71-76
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• 2015

Recently, light emitting diodes (LEDs) have been studied to improve their efficiencies for the uses in various fields. Particularly in the aspect of chip structure, via hole type vertical LED chip is developed for improvement of light output power, and heat dissipations. However, current vertical type LEDs have still drawback, which is current concentration around the n-contact holes. In this research, to solve this phenomenon, we introduced isolation layer under n-contact electrodes. With this sub-electrode, even though the active area was decreased by about 2.7% compared with conventional via-hole type vertical LED, we could decrease the forward voltage by 0.2 V and wall-plug efficiency was improved approximately 4.2%. This is owing to uniform current flow through the area of n-contact.

• Journal of the Microelectronics and Packaging Society
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• v.22 no.4
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• pp.99-104
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• 2015

The requirement for success of via filling is its ability to fill via holes completely without producing voids or seams. Defect free via filling was obtained by optimizing plating conditions such as current mode, current density and additives. However, byproducts stemming from the breakdown of these organic additives reduce the lifetime of the devices and plating solutions. In this study, the relationship between JGB and current density on the copper via filling was investigated without the addition of other additives to minimize the contamination of copper via. AR 4 with $15{\mu}m$ diameter via were used for this study. The pulse current was used for the electroplating of copper and the current densities were varied from 10 to $20mA/cm^2$ and the concentrations of JGB were varied from 0 to 25 ppm. The map for the JGB concentration and current density was developed. And the optimum conditions for the AR 4 via filling with $15{\mu}m$ diameter were obtained.

• Transactions on Electrical and Electronic Materials
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• v.6 no.3
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• pp.87-90
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• 2005

$SiO_2$ via-hole etching with a high aspect ratio is a key process in fabricating ULSI devices; however, accumulated charge during plasma etching can cause etching stop, micro-loading effects, and charge build-up damage. To alleviate this concern, charge-up damage sensor was fabricated for the ultimate goal of real-time monitoring of accumulated charge. As an effort to reach the ultimate goal, fabricated sensor was used for electrical potential measurements of via holes between two poly-Si electrodes and roughly characterized under various plasma conditions using statistical design of experiment (DOE). The successful identification of potential difference under various plasma conditions not only supports the evidence of potential charge-up damage, but also leads the direction of future study.