• Proceedings of the Ginseng society Conference
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• 1978.09a
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• pp.29-40
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• 1978

• Journal of KIISE:Computer Systems and Theory
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• v.31 no.5_6
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• pp.371-378
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• 2004

This paper presents the implementation and performance of the HVIA-GE card, which is a hardware implementation of the Virtual Interface Architecture (VIA) based on Gigabit Ethernet. The HVIA-GE card is a 32-bit/33MHz PCI adapter containing an FPGA for the VIA protocol engine and a Gigabit Ethernet chip set to construct a high performance physical network. HVIA-GE performs virtual-to-physical address translation, Doorbell, and send/receive completion operations in hardware without kernel intervention. In particular, the Address Translation Table (ATT) is stored on the local memory of the HVIA-GE card, and the VIA protocol engine efficiently controls the address translation process by directly accessing the ATT. As a result, the communication overhead during send/receive transactions is greatly reduced. Our experimental results show the maximum bandwidth of 93.7MB/s and the minimum latency of 11.9${\mu}\textrm{s}$. In terms of minimum latency HVIA-GE performs 4.8 times and 9.9 times faster than M-VIA and TCP/IP, respectively, over Gigabit Ethernet. In addition, the maximum bandwidth of HVIA-GE is 50.4% and 65% higher than M-VIA and TCP/IP respectively.

• Proceedings of the Korean Institute of Surface Engineering Conference
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• 2016.11a
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• pp.128-128
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• 2016

Cu 배선폭 미세화 기술은 반도체 디바이스의 성능 향상을 위한 핵심 기술이다. 현재 배선 기술은 lithography, deposition, planarization등 종합적인 공정 기술의 발전에 따라 10x nm scale까지 감소하였다. 하지만 지속적인 feature size 감소를 위하여 요구되는 높은 공정 기술 및 비용과 배선폭 미세화로 인한 재료의 물리적 한계로 인하여 배선폭 미세화를 통한 성능의 향상에는 한계가 있다. 배선폭 미세화를 통한 2차원적인 집적도 향상과는 별개로 chip들의 3차원 적층을 통하여 반도체 디바이스의 성능 향상이 가능하다. 칩들의 3차원 적층을 위해서는 별도의 3차원 배선 기술이 요구되는데, TSV(through-Si-via)방식은 Si기판을 관통하는 via를 통하여 chip간의 전기신호 교환이 최단거리에서 이루어지는 가장 진보된 형태의 3차원 배선 기술이다. Si 기판에 $50{\mu}m$이상 깊이의 via 및 seed layer를 형성 한 후 습식전해증착법을 이용하여 Cu 배선이 이루어지는데, via 내부 Cu ion 공급 한계로 인하여 일반적인 공정으로는 void와 같은 defect가 형성되어 배선 신뢰성에 문제를 발생시킨다. 이를 해결하기 위해 각종 유기 첨가제가 사용되는데, suppressor를 사용하여 Si 기판 상층부와 via 측면벽의 Cu 증착을 억제하고, accelerator를 사용하여 via 바닥면의 Cu 성장속도를 증가시켜 bottom-up TSV filling을 유도하는 방식이 일반적이다. 이론적으로, Bottom-up TSV filling은 sample 전체에서 Cu 성장을 억제하는 suppressor가 via bottom의 강한 potential로 인하여 국부적 탈착되고 via bottom에서만 Cu가 증착되어 되어 이루어지므로, accelerator가 없이도 void-free TSV filling이 가능하다. Accelerator가 Suppressor를 치환하여 오히려 bottom-up TSV filling을 방해한다는 보고도 있었다. 본 연구에서는 유기 첨가제의 치환으로 인한 TSV filling performance 저하를 방지하고, 유기 첨가제 조성을 단순화하여 용액 관리가 용이하도록 하기 위하여 suppressor만을 이용한 TSV filling 연구를 진행하였다. 먼저, suppressor의 흡착, 탈착 특성을 이해하기 위한 연구가 진행되었고, 이를 바탕으로 suppressor만을 이용한 bottom-up Cu TSV filling이 진행되었다. 최종적으로 $60{\mu}m$ 깊이의 TSV를 1000초 내에 void-free filling하였다.

• Asian Pacific Journal of Cancer Prevention
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• v.16 no.6
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• pp.2327-2331
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• 2015

Purpose: To determine the accuracy of visual inspection with acetic acid (VIA) in detecting high-grade cervical intraepithelial neoplasia (CIN) in pre- and post-menopausal women with atypical squamous cells of undetermined significance (ASC-US) and low grade squamous intraepithelial lesion (LSIL) Papanicolaou (Pap) smears. Materials and Methods: Two hundred women (150 pre-menopausal and 50 post-menopausal) with ASC-US and LSIL cytology who attended the colposcopy clinic, Thammasat University Hospital, between March 2013 and August 2014 were included. All women underwent VIA testing and colposcopy by gynecologic oncologists. Diagnostic values of VIA testing including sensitivity, specificity, positive predictive value (PPV) and negative predictive value (NPV) for detecting high-grade CIN were determined using the histopathology obtained from colposcopic-directed biopsy as a gold standard. Results: VIA testing was positive in 54/150 (36%) pre-menopausal women and 5/50 (10%) post-menopausal women. Out of 54 pre-menopausal women with positive VIA testing, 15 (27.8%) had high-grade CIN and 39 (72.2%) had either CIN 1 or insignificant pathology. Ten (10.4%), 43 (44.8%) and 43 (44.8%) out of the remaining 96 pre-menopausal women with negative VIA testing had high-grade CIN, CIN 1 and insignificant pathology, respectively. Out of 5 post-menopausal women with positive VIA testing, there were 4 (80%) women with high-grade CIN, and 1 (20%) women with insignificant pathology. Out of 45 VIA-negative post-menopausal women, 42 (93.3%) women had CIN 1 and insignificant pathology, and 3 (6.7%) had high-grade CIN. Sensitivity, specificity, PPV and NPV of the VIA testing were 59.4%, 76.2%, 32.2% and 90.8%, respectively (60%, 68.8%, 27.8% and 89.6% in pre-menopausal women and 57.1%, 97.7%, 80% and 93.3% in post-menopausal women). Conclusions: VIA testing may be used as a screening tool for detecting high-grade CIN in women with minor cervical cytological abnormalities in a low-resource setting in order to lower the rate of colposcopy referral.

• The Journal of Korean Academy of Prosthodontics
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• v.41 no.1
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• pp.20-34
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• 2003

Novel methods producing supplementary and prosthetic material by cutting or discharge processing via computer design have been proposed as alternatives for traditional casting methods and are being utilized for commercial purposes. The CAD/CAM system used in dentistry can be classified into three-dimensional input of target values, restoration design, and material processing. The marginal fidelity in production of In-Ceram core has important clinical implications and is a key consideration issue in CAD/CAM production as well. Through this research, the author arrived at the following conclusion aaer conducting comparison analysis of marginal fidelities between the In-Ceram core produced via CAD/CAM and that produced through the traditional method ; 1. In the cases of mesial, distal, and lingual margins, the core margins via CAD/CAM produced lower values than those via the traditional method, but the differences were found to be statistically insignificant. 2. In the case of labial flange, the core margins via CAD/CAM produced lower values than those via the traditional method and the differences were found to be statistically significant. (p<0.05) 3. In comparision with overall marginal fidelity, the core margins via CAD/CAM produced lower values than those via the traditional method, but the differences were found to be statistically insignificant. 4. Among the core margins produced via the traditional method did not have statistically significant differences but fir those produced via CAD/CAM had statistically significant differences between labial and lingual sides and between labial and mesial sides. (p <0.05).

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.2
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• pp.61-66
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• 2011

A new via structure on printed circuit board has been proposed for differential signaling in applications of high-speed interconnection. In new structure, the via is physically separated and then divided into two electrically-isolated sections using mechanical drill routing process. These cutted vias are connected respectively to the traces of the differential pair. New via structure makes possible to rout the differential pair using only one via, while conventional via structure needs two vias for interconnection. Because the spacing even in via region keeps almost constant, new via structure can alleviate an impedance discontinuity and then enhance its signal transmission characteristics such as reflection loss and insertion loss. It is expected that new via structure is effective in differential signaling for high-speed interconnection.

• 제어로봇시스템학회:학술대회논문집
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• 1997.10a
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• pp.227-230
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• 1997

In this paper, robot navigation experiments with a new navigation algorithm are carried out in real environments. The authors already proposed a reactive navigation algorithm for mobile robots using optimal via-point selection method. At each sampling time, a number of via-point candidates is constructed with various candidates of heading angles and velocities. The robot detects surrounding obstacles, and the proposed algorithm utilizes fuzzy multi-attribute decision making in selecting the optimal via-point the robot would proceed at next step. Fuzzy decision making allows the robot to choose the most qualified via-point even when the two navigation goals-obstacle avoidance and target point reaching-conflict each other. The experimental result shows the successful navigation can be achieved with the proposed navigation algorithm for real environments.

• Journal of Electrical Engineering and Technology
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• v.6 no.2
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• pp.280-283
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• 2011

In the present work, a new approach is proposed for via interconnects of semiconductor devices, where multi-wall carbon nanotubes (MWCNTs) are used instead of conventional metals. In order to implement a selective growth of carbon nanotubes (CNTs) for via interconnect, the buried catalyst method is selected which is the most compatible with semiconductor processes. The cobalt catalyst for CNT growth is pre-deposited before via hole patterning, and to achieve the via etch stop on the thin catalyst layer (ca. 3nm), a novel 2-step etch scheme is designed; the first step is a conventional oxide etch while the second step chemically etches the silicon nitride layer to lower the damage of the catalyst layer. The results show that the 2-step etch scheme is a feasible candidate for the realization of CNT interconnects in conventional semiconductor devices.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2010.06a
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• pp.201-201
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• 2010

볼로미터 제작 공정 중 One step via 공정 시 via hole 모양에 의해 정기적 연결 및 구조적 안정성에 문제를 해결하기 위하여 다른 via 식각 방식으로 공정을 진행하였으며 그에 따른 via 공정 차이에 대한 결과를 연구하였다.

• Journal of the Microelectronics and Packaging Society
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• v.24 no.1
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• pp.35-43
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• 2017

The three-dimensional integrated circuit (3D-IC) is a general trend for the miniaturized and high-performance electronic devices. The through-silicon-via (TSV) is the advanced interconnection method to achieve 3D integration, which uses vertical metal via through silicon substrate. However, the TSV based 3D-IC undergoes severe thermo-mechanical stress due to the CTE (coefficient of thermal expansion) mismatch between via and silicon. The thermo-mechanical stress induces mechanical failure on silicon and silicon-via interface, which reduces the device reliability. In this paper, the thermo-mechanical reliability of TSV based 3D-IC is reviewed in terms of mechanical fracture, heat conduction, and material characteristic. Furthermore, the state of the art via-level and package-level design techniques are introduced to improve the reliability of TSV based 3D-IC.