• Journal of international Conference on Electrical Machines and Systems
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• 제3권1호
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• pp.40-47
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• 2014

Sinusoidal back-EMF waveform of vernier Permanent Magnet (PM) machines is analyzed in this paper. An analytical expression of Electromotive Force (EMF) of electric machines including vernier machines is developed to analyze EMF harmonics, and the effect of vernier PM machine pole ratio, the ratio of number of rotor poles to stator poles, on the EMF waveform. Moreover, this paper represents several Finite Element Analysis (FEA) models to verify the analysis based on the proposed expression, and the effect of tooth width ratio, which is the ratio of tooth width to tooth pitch, on back-EMF of vernier PM machines, and optimal tooth width ratio is obtained and verified by FEA. Finally, this paper makes comparisons between EMF waveform of vernier PM machines and that of traditional PM machines from the point of view of analytical EMF expression.

• 전력전자학회논문지
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• 제5권1호
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• pp.54-62
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• 2000

본 논문은 Vernier 모드에서 운전하는 2-모듈 TCSC로 구성된 전력송전시스템의 특성 해석을 위하여 싸이리스터 점호각 계산을 푸리에 공간에서 수행한다. 이를 위하여 싸이리스터 스위칭 함수를 이용하여 TCSC 리액터 전류에 관한 연립방정식을 구하였다. TCSC 모듈의 등가 임피던스가 전력송전 시스템이 요구하는 특정값을 갖게 하는 싸이리스터 점호각을 수치해석 방법을 사용하여 구하고, TCSC 전력송전시스템의 정상상태 특성을 해석하였다. 또한 EMTP 시뮬레이션을 수행하여 푸리에 공간에서의 점호각 계산의 타당성을 시평면상에서 검증하였다.

• 한국정보통신학회논문지
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• 제17권3호
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• pp.546-555
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• 2013

본 연구에서는 수동소나 신호의 분석에서 얻어지는 토널 성분, 즉, 주파수선의 하모닉 성분을 강화하는 새로운 방법을 제안하였다. 제안한 방법에서는, 먼저 스펙트럼의 일정 시간에 따른 주파수 빈별 평균값을 구하고, 평균값과의 차이를 이용하여 안정적인 주파수선과 불안정한 주파수선을 구별한다. 그런 다음 불안정한 주파수선에 자기상관함수와 S2PM을 적용하여 배경잡음을 줄이고 하모닉 성분을 강조하게 된다. 실제 어선에서 획득한 수중음향 데이터를 이용한 실험 결과를 분석하였고, 이를 통해 제안한 방법의 타당성을 검증하였다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2000년도 추계종합학술대회 논문집(2)
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• pp.83-86
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• 2000

This paper describes a delay-locked loop(DLL_) with low-jitter using Vernier Method. This DLL can be used to synchronize the internal clock to the external clock with very short time interval and fast lock-on. The proposed circuit was simulated in a 0.25 $\mu\textrm{m}$ CMOS technology to realize low-jitter. We verified 50-ps of time interval within 5 clock cycles of the clock as the simulation results.

• 전자공학회논문지
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• 제52권2호
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• pp.195-200
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• 2015

본 논문에서는 ADPLL의 잡음 개선을 위해 8비트 SVBS-TDC (Semi-Vernier Binary-Search Time-to-Digital Converter)를 제안했다. TDC의 동작 속도를 높이기 위해 인코더 등 디지털 블록을 사용하지 않는 BS-TDC (Binary-Search TDC) 구조를 사용했으며, 버니어 구조를 적용하여 기존의 BS-TDC에 비해 해상도를 10배 이상 증가시켰다. TDC의 단점인 좁은 입력범위를 개선하기 위해 버니어 구조를 절반만 적용하여 510ps의 넓은 입력 범위를 확보했다. 제안하는 SVBS-TDC는 65nm CMOS 공정으로 설계하였고, 모의실험 결과 1.2V 전원 전압에서 동작 속도는 200MHz이고 해상도는 4ps로서 ADPLL의 잡음 특성을 효과적으로 개선함을 확인하였다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제12권4호
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• pp.411-417
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• 2012

A Coarse-Fine Time-to-Digital Converter (TDC) using the single time amplifier is proposed. A vernier delay line is used to overcome process dependency and the 2-stage time amplifier is designed to have high resolution by increasing the gain of the time amplifier. Single time amplifier architecture reduces the silicon area of the TDC and alleviates mismatch effect between time amplifiers. The proposed TDC is implemented in $0.18{\mu}m$ CMOS process with the supply voltage of 1.8 V. The measured results show that the resolution of the TDC is 0.73 ps with 10-bit digital output, although highend process is not applied. The single time amplifier architecture reduces 13% of chip area compared to previous work. By reducing the supply voltage, the linearity of the TDC is enhanced and the resolution is decreased to 1.45 ps.

• Journal of Electrical Engineering and Technology
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• 제11권6호
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• pp.1700-1706
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• 2016

In this paper, a dual-stator, spoke-type linear vernier machine (DSSLVM) for wave energy extraction application was proposed. This machine is capable of producing a competitively high thrust force and force density at a low operation speed in direct drive systems. The operation principal and working of the proposed DSSLVM were studied. The stator core height is adjusted to improve the overall force density of the proposed machine while reducing the force ripple. To evaluate the advantages of the proposed DSSLVM, the main performance was compared with that of a recently developed linear primary permanent magnet vernier machine (LPPMVM). The proposed machine exhibited greater thrust force and force density, an improved power factor and lower force ripple with the same permanent magnet (PM) volume compared to the LPPMVM.

• Journal of Electrical Engineering and Technology
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• 제11권1호
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• pp.150-156
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• 2016

This paper compares the performances of permanent-magnet synchronous (PMS) and permanent-magnet vernier (PMV) machines for low-speed and high-torque applications. For comparison with the PMS machines, we consider two types of the PMV machine. The first one has surface-mounted permanent magnets (PMs) on the rotor and the other has PMs inserted on both sides of the stator and rotor. The PMS and PMV machines are designed to meet the condition of equal output power per unit volume. We analyze the magnetic fields of the machines using a two-dimensional finite element analysis (FEA). We then compare their performances in terms of the generated torque characteristics, power factor, loss, and efficiency.

• Journal of Electrical Engineering and Technology
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• 제8권5호
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• pp.1146-1151
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• 2013

This paper deals with design consideration and validation of a new pole-slot combination for permanent magnet vernier machine (PMVM) with consequent pole (CP) rotor especially for extremely low speed servo applications. A 136pole-24slot PMVM with CP rotor is introduced and analyzed by 2D and 3D finite element analysis (FEA) and discussion on experimental validation is also included.

• 전기전자학회논문지
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• 제10권1호
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• pp.16-21
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• 2006

본 논문은 PLL구조에서 새로운 버니어 지연 VCO구조를 이용한 다중위상 발생회로를 서술하였다. 제안하는 기법은 VCO의 지연단의 지연보다 더 미세한 타이밍신호를 만들어낸다. 0.18um CMOS공정을 이용하여 칩 제작 후 측정결과 1GHz에서 약 62.5ps의 위상정밀도를 갖는 신호를 만들었고 지터는 14ps로 측정되었다.