• Journal of the Institute of Electronics and Information Engineers
• /
• v.52 no.12
• /
• pp.99-108
• /
• 2015

The embedded microcontroller which is operated by the logic gates synchronized on the clock pulse, is gradually used as main controller of mission-critical systems. Severe electrical situations such as high voltage/frequency surge may cause malfunctioning of the clock source. The tolerant system operation is required against the various external electric noise and means the robust design technique is becoming more important issue in system clock failure problems. In this paper, we propose on-chip backup clock change architecture for the automatic clock failure detection. For the this, we adopt the edge detector, noise canceller logic and glitch-free clock changer circuit. The implemented edge detector unit detects the abnormal low-frequency of the clock source and the delay chain circuit of the clock pulse by the noise canceller can cancel out the glitch clock. The externally invalid clock source by detecting the emergency status will be switched to back-up clock source by glitch-free clock changer circuit. The proposed circuits are evaluated by Verilog simulation and the fabricated IC is validated by using test equipment electrical field radiation noise

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.44 no.4
• /
• pp.55-62
• /
• 2007

This paper proposes a defective pixel detection algorithm and its hardware structure for CCD/CMOS image sensor. In previous algorithms, the characteristics of image have not been considered. Also, some algorithms need quite a time to detect defective pixels. In order to make up for those disadvantages, the proposed defective pixel detection method detects defective pixels efficiently by considering the edges in the image and verifies them using several frames while checking scene-changes. Whenever scene-change is occurred, potentially defective pixels are checked and confirmed whether it is defective or not. Test results showed that the correct detection rate in a frame was increased 6% and the defective pixel verification time was decreased 60%. The proposed algorithm was implemented with verilog HDL. The edge indicator in color interpolation block was reused. Total logic gate count was 5.4k using 0.25um CMOS standard cell library.

• Journal of the Institute of Electronics and Information Engineers
• /
• v.50 no.11
• /
• pp.58-63
• /
• 2013

This paper presents a transceiver design for DisplayPort interface using an optical channel. By converting the electronic channel to the optical channel, the DisplayPort's main channel can provide a high-speed data transmission for long distance. The design converting the electronic channel to the optical channel in the main channel and AUX channel of the DisplayPort is presented in this paper. Futhermore, the HPD signal transmission by using AUX channel is proposed. In order to minimize power consumption, this paper also proposed a method of controlling the TX block in the main link. The proposed system is designed by a FPGA and an optical module. The FPGA used 651 ALUT(adaptive look-up table)s, 511 resisters and 324 block memory bits. The maximum operating rate of the FPGA is 250MHz. With the proposed power control scheme, 740mW of power dissipation reduction can be achieved at the main link optical TX module.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2011.10a
• /
• pp.431-435
• /
• 2011

This paper presents optimized searching technique to improve the performance of H.264/AVC. The proposed CAVLC encoder uses forward and backward searching algorithm to compute the parameters. By zero-block skipping technique and pipelined scheduling, the proposed CAVLC encoder can obtain better performance. The experimental result shows that the proposed architecture needs only 66.6 cycles on average for each $16{\times}16$ macroblock encoding. The proposed architecture improves the performance by 13.8% than that of previous designs. The proposed CAVLC encoder was implemented using VerilogHDL and synthesized with Megnachip $0.18{\mu}m$ standard cell library. The synthesis result shows that the gate count is about 15.6K with 125Mhz clock frequency.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.18 no.9
• /
• pp.2109-2116
• /
• 2014

This paper presents the implementation and design of the advanced WI-FI systems with beam-forming antenna that radiate their power to the direction of user equipment to improve the overall throughput, contrast to the general WI-FI systems equipped with omni-antenna. The system consists of patch array antenna, DSP, FPGA, and Qualcomm's commercial chip. The beam-forming system on the FPGA utilizes the packet information from Qualcomm's commercial chip to control the phase shifters and attenuators of the patch array antenna. The PCI express interface has been used to maximize the communication speed between DSP and FPGA. The directions of arrival of users are managed using the database, and each user is distinguished by the MAC address given from the packet information. When the system wants to transmit a packet to one user, it forms beams to the direction of arrival of the corresponding user stored in the database to maximize the throughput. Directions of arrival of users are estimated using the received preamble in the packet to make its SINR as high as possible. The proposed beam-forming system was implemented using an FPGA and Qualcommm's commercial chip together. The implemented system showed considerable throughput improvement over the existing general AP system with omni-directional antenna in the multi-user communication environment.

• Journal of Advanced Information Technology and Convergence
• /
• v.9 no.1
• /
• pp.115-125
• /
• 2019

In this paper, the image is received from the camera and the lane is sensed. There are various ways to detect lanes. Generally, the method of detecting edges uses a lot of the Sobel edge detection and the Canny edge detection. The minimum use of multiplication and division is used when designing for the hardware configuration. The images are tested using a black box image mounted on the vehicle. Because the top of the image of the used the black box is mostly background, the calculation process is excluded. Also, to speed up, YCbCr is calculated from the image and only the data for the desired color, white and yellow lane, is obtained to detect the lane. The median filter is used to remove noise from images. Intermediate filters excel at noise rejection, but they generally take a long time to compare all values. In this paper, by using addition, the time can be shortened by obtaining and using the result value of the median filter. In case of the Sobel edge detection, the speed is faster and noise sensitive compared to the Canny edge detection. These shortcomings are constructed using complementary algorithms. It also organizes and processes data into parallel processing pipelines. To reduce the size of memory, the system does not use memory to store all data at each step, but stores it using four line buffers. Three line buffers perform mask operations, and one line buffer stores new data at the same time as the operation. Through this work, memory can use six times faster the processing speed and about 33% greater quantity than other methods presented in this paper. The target operating frequency is designed so that the system operates at 50MHz. It is possible to use 2157fps for the images of 640by360 size based on the target operating frequency, 540fps for the HD images and 240fps for the Full HD images, which can be used for most images with 30fps as well as 60fps for the images with 60fps. The maximum operating frequency can be used for larger amounts of the frame processing.