• Journal of the Institute of Electronics Engineers of Korea SD
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• v.49 no.1
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• pp.25-34
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• 2012

This paper presents a universal architecture for variable-length eight-parallel Reed-Solomon (RS) decoder for high-rate WPAN systems. The proposed architecture can support not only RS(255,239) code but various shortened RS codes. Moreover, variable-length architecture provides variable low latency for various shortened RS codes and the eight-parallel design also provides high data processing rate. Using 90-$nm$ CMOS standard cell technology, the proposed RS decoder has been synthesized and measured for performance. The proposed RS decoder can provide a maximum 19-$Gbps$ data rate at clock frequency 300 $MHz$.

• Proceedings of the IEEK Conference
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• 2001.06a
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• pp.113-116
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• 2001

Reed-Solomon(RS) code is the most powerful burst error correcting code. In Ois paper, the architecture for the adaptive RS encoder adaptable for multi QoS requirements or time-varying channel environments has been designed. In the adaptive RS code, the message length k and the error correction capability t are allowed to be variable so that the block length n is also variable. We proposed the architecture of the adaptive RS encoder by designing the optimal structure of Galois fields multiplier with comparison of fixed multiplier and variable multiplier. The proposed architecture is implemented in VHDL and verified with the simulation tool

• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.8C
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• pp.763-770
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• 2006

In this paper, a variable Reed-Solomon(RS) decoder with erasure decoding functionality is designed based on the modified Euclid's algorithm(MEA). The variability of the decoder is implemented through shortening and puncturing based on the RS(124, 108, 8) code, other than the primitive RS(255, 239, 8) code. This leads to shortening the decoding latency. The decoder performs 4-step pipelined operation, where each step is designed to be clocked by an independent clock. Thus by using a faster clock for the MEA block, the complexity and the decoding latency can be reduced. It can support both continuous- and burst-mode decoding. It has been designed in VHDL and synthesized in an FPGA chip, consuming 3,717 logic cells and 2,048-bit memories. The maximum decoding throughput is 33 MByte/sec.

• Journal of information and communication convergence engineering
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• v.2 no.3
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• pp.139-144
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• 2004

In order to transmit various types of multimedia data (i.e. voice, video, and data) over a wireless channel, the coding and modulation scheme needs to be flexible and capable of providing a variable quality of service, data rates, and latency. In this paper, we study a mobile multimedia COMA network combined with the concatenated Reed-Solomon/Rate Compatible Punctured Convolution code (RS/RCPC). Also, this paper propose the combination of concatenated RS/RCPC coder and COMA RAKE receiver for multimedia COMA traffic which can be sent over wireless channels. From the results, using a frequency selective Rayleigh fading channel model, it is shown that concatenated RS/RCPC coder at the wireless physical layer can be effective in providing reliable wireless multimedia CDMA network. And the proposed scheme that combine concatenated RS/RCPC coder and CDMA RAKE receiver provides a significant gain in the BER performance over multi-user interference and multipath frequency selective fading channels.

• Proceedings of the IEEK Conference
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• 2003.07a
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• pp.549-552
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• 2003

In this paper, an efficient architecture of a versatile Reed-Solomon (RS) decoder is designed, where the message length k as well as the block length n can be variable. The decoder permits 3-step pipelined processing based on the modified Euclid's algorithm(MEA). A new architecture for the MEA is designed for variable values of error correcting capability t. To maintain the throughput rate with less circuitry, the MEA block uses both the recursive and the overclocking technique. The decoder can decode a codeword received not only in a burst mode, but also in a continuous mode. It can be used in a wide range of applications due to its versatility. A versatile RS decoder over GF(2$^{8}$ ) having the error-correcting capability of up to 10 has been designed in VHDL, and successfully synthesized in an FPGA chip.

• Journal of Astronomy and Space Sciences
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• v.36 no.2
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• pp.75-86
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• 2019

UV Psc is a typical RS CVn type system undergoing dynamic chromosphere activity. We performed photometric observations of the system in 2015 and secured new BVR light curves showing well-defined photometric waves. In this paper, we analyzed the light curves using Wilson-Devinney binary code and investigated the orbital period of the system. The combination of our light curve synthesis with the spectroscopic solution developed by previous investigators yielded the absolute parameters as: $M_1=1.104{\pm}0.042M_{\odot}$, $R_1=1.165{\pm}0.025R_{\odot}$, and $L_1=1.361{\pm} 0.041L_{\odot}$ for the primary star, and $M_2=0.809{\pm}0.082M_{\odot}$, $R_2=0.858{\pm}0.018R_{\odot}$, and $L_2=0.339 {\pm}0.010L_{\odot}$ for the secondary star. The eclipse timing diagram for accurate CCD and photoelectric timings showed that the orbital period may vary either in a downward parabolic manner or a quasi-sinusoidal pattern. If the latter is adopted as a probable pattern for the period change, a more plausible account for the cyclic variation may be the light time effect caused by a circumbinary object rather than an Applegate-mechanism occurring via variable surface magnetic field strengths.