• Smart Media Journal
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• v.3 no.1
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• pp.39-45
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• 2014

The partial product matrix of a parallel squarer are symmetric about the diagonal. To reduce the number of partial product bits and the depth of partial product matrix, it can be typically folded, shifted and bit-rearranged. In this paper, an efficient design approach for the combined squarer, capable of operating on either unsigned or signed numbers based on a mode selection signal, is presented. By simulations, it is shown that the proposed combined squarers lead to up to 18% reduction in area, 11% reduction in propagation delay and 9% reduction in power consumption compared with the previous combined squarers.