• Title/Summary/Keyword: two-step interpolation

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Climate Change Impact on the Flowering Season of Japanese Cherry (Prunus serrulata var. spontanea) in Korea during 1941-2100 (기후변화에 따른 벚꽃 개화일의 시공간 변이)

  • Yun Jin-I.
    • Korean Journal of Agricultural and Forest Meteorology
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    • v.8 no.2
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    • pp.68-76
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    • 2006
  • A thermal time-based two-step phenological model was used to project flowering dates of Japanese cherry in South Korea from 1941 to 2100. The model consists of two sequential periods: the rest period described by chilling requirement and the forcing period described by heating requirement. Daily maximum and minimum temperature are used to calculate daily chill units until a pre-determined chilling requirement for rest release is met. After the projected rest release date, daily heat units (growing degree days) are accumulated until a pre-determined heating requirement for flowering is achieved. Model calculations using daily temperature data at 18 synoptic stations during 1955-2004 were compared with the observed blooming dates and resulted in 3.9 days mean absolute error, 5.1 days root mean squared error, and a correlation coefficient of 0.86. Considering that the phonology observation has never been fully standardized in Korea, this result seems reasonable. Gridded data sets of daily maximum and minimum temperature with a 270 m grid spacing were prepared for the climatological years 1941-1970 and 1971-2000 from observations at 56 synoptic stations by using a spatial interpolation scheme for correcting urban heat island effect as well as elevation effect. A 25km-resolution temperature data set covering the Korean Peninsula, prepared by the Meteorological Research Institute of Korea Meteorological Administration under the condition of Inter-governmental Panel on Climate Change-Special Report on Emission Scenarios A2, was converted to 270 m gridded data for the climatological years 2011-2040, 2041-2070 and 2071-2100. The model was run by the gridded daily maximum and minimum temperature data sets, each representing a climatological normal year for 1941-1970, 1971-2000, 2011-2040, 2041-2070, and 2071-2100. According to the model calculation, the spatially averaged flowering date for the 1971-2000 normal is shorter than that for 1941-1970 by 5.2 days. Compared with the current normal (1971-2000), flowering of Japanese cherry is expected to be earlier by 9, 21, and 29 days in the future normal years 2011-2040, 2041-2070, and 2071-2100, respectively. Southern coastal areas might experience springs with incomplete or even no Japanese cherry flowering caused by insufficient chilling for breaking bud dormancy.

GPU-based dynamic point light particles rendering using 3D textures for real-time rendering (실시간 렌더링 환경에서의 3D 텍스처를 활용한 GPU 기반 동적 포인트 라이트 파티클 구현)

  • Kim, Byeong Jin;Lee, Taek Hee
    • Journal of the Korea Computer Graphics Society
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    • v.26 no.3
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    • pp.123-131
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    • 2020
  • This study proposes a real-time rendering algorithm for lighting when each of more than 100,000 moving particles exists as a light source. Two 3D textures are used to dynamically determine the range of influence of each light, and the first 3D texture has light color and the second 3D texture has light direction information. Each frame goes through two steps. The first step is to update the particle information required for 3D texture initialization and rendering based on the Compute shader. Convert the particle position to the sampling coordinates of the 3D texture, and based on this coordinate, update the colour sum of the particle lights affecting the corresponding voxels for the first 3D texture and the sum of the directional vectors from the corresponding voxels to the particle lights for the second 3D texture. The second stage operates on a general rendering pipeline. Based on the polygon world position to be rendered first, the exact sampling coordinates of the 3D texture updated in the first step are calculated. Since the sample coordinates correspond 1:1 to the size of the 3D texture and the size of the game world, use the world coordinates of the pixel as the sampling coordinates. Lighting process is carried out based on the color of the sampled pixel and the direction vector of the light. The 3D texture corresponds 1:1 to the actual game world and assumes a minimum unit of 1m, but in areas smaller than 1m, problems such as stairs caused by resolution restrictions occur. Interpolation and super sampling are performed during texture sampling to improve these problems. Measurements of the time taken to render a frame showed that 146 ms was spent on the forward lighting pipeline, 46 ms on the defered lighting pipeline when the number of particles was 262144, and 214 ms on the forward lighting pipeline and 104 ms on the deferred lighting pipeline when the number of particle lights was 1,024766.

A 10b 50MS/s Low-Power Skinny-Type 0.13um CMOS ADC for CIS Applications (CIS 응용을 위해 제한된 폭을 가지는 10비트 50MS/s 저 전력 0.13um CMOS ADC)

  • Song, Jung-Eun;Hwang, Dong-Hyun;Hwang, Won-Seok;Kim, Kwang-Soo;Lee, Seung-Hoon
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.48 no.5
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    • pp.25-33
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    • 2011
  • This work proposes a skinny-type 10b 50MS/s 0.13um CMOS three-step pipeline ADC for CIS applications. Analog circuits for CIS applications commonly employ a high supply voltage to acquire a sufficiently acceptable dynamic range, while digital circuits use a low supply voltage to minimize power consumption. The proposed ADC converts analog signals in a wide-swing range to low voltage-based digital data using both of the two supply voltages. An op-amp sharing technique employed in residue amplifiers properly controls currents depending on the amplification mode of each pipeline stage, optimizes the performance of op-amps, and improves the power efficiency. In three FLASH ADCs, the number of input stages are reduced in half by the interpolation technique while each comparator consists of only a latch with low kick-back noise based on pull-down switches to separate the input nodes and output nodes. Reference circuits achieve a required settling time only with on-chip low-power drivers and digital correction logic has two kinds of level shifter depending on signal-voltage levels to be processed. The prototype ADC in a 0.13um CMOS to support 0.35um thick-gate-oxide transistors demonstrates the measured DNL and INL within 0.42LSB and 1.19LSB, respectively. The ADC shows a maximum SNDR of 55.4dB and a maximum SFDR of 68.7dB at 50MS/s, respectively. The ADC with an active die area of 0.53$mm^2$ consumes 15.6mW at 50MS/s with an analog voltage of 2.0V and two digital voltages of 2.8V ($=D_H$) and 1.2V ($=D_L$).