• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2001.10a
• /
• pp.621-625
• /
• 2001

In this article, piezoelectric films and their application for film bulk acoustic resonator (FBAR) devices are presented. The FBAR is composed of piezoelectric film sandwiched between top and bottom electrodes and an acoustic reflector of SiO$_2$/W slatted multilayers. Various FBAR devices were fabricated and evaluated through simulation and measurement. The insertion loss, return loss and Q-factor were observed to be reasonably high and good. The FBAR technology seems very promising particularly for RF band filter application.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2003.11a
• /
• pp.360-363
• /
• 2003

In this paper, we investigated SiNx film as a buffer layer of TFT-FRAM. Buffer layers were prepared by two step process of a $N_2$ plasma treatment and subsequent $SiN_x$ deposition. By employing $N_2$ plasma treatment, interface traps such as mobile charges and injected charges were removed, hysteresis of current-voltage curve disappeared. After $N_2$ plasma treatment, a leakage current was decreased about 2 orders. From these results, it is possible to perform the plasma treating process to make a good quality buffer layer of MFIS-FET or capacitor as an application of non-volatile memory.

• Journal of Ceramic Processing Research
• /
• v.13 no.spc1
• /
• pp.59-63
• /
• 2012

Ga2O3-core/CdO-shell nanowires were synthesized by a two step process comprising thermal evaporation of GaN powders and sputter-deposition of CdO. Transmission electron microscopy (TEM) and X-ray diffraction (XRD) analyses revealed that the cores and the shells of the annealed coaxial nanowires were single crystal of monoclinic Ga2O3 and FCC CdO, respectively. As-synthesized Ga2O3 nanowires showed a broad emission band at approximately 460 nm in the blue region. The blue emission intensity of the Ga2O3 nanowires was slightly decreased by CdO coating, but it was significantly increased by subsequent thermal annealing in a reducing atmosphere. The major emission peak was also shifted from ~500 nm by annealing in a reducing atmosphere, which is attributed to the increases in the Cd interstitial and O vacancy concentrations in the cores.

• Proceedings of the Materials Research Society of Korea Conference
• /
• 2003.11a
• /
• pp.235-235
• /
• 2003

The development of a buffer layer is an important issue for the second -generation wire, YBCO coated metal wire. The buffer layer demands not only on the prohibition of the reaction between YBCO and metal substrate, but also the proper lattice match and conductivity for high critical current density (Jc) of YBCO superconductor, In order to satisfy these demands, we suggested CaRuO3 as a useful candidate having that the lattice mismatches with Ni (200) and with YBCO are 8.2% and 8.0%, respectively. The CaRuO3 thin films were deposited on Ni substrates using various methods, such as e-beam evaporation and DC and RF magnetron sputtering. These films were investigated using SEM, XRD, pole-figure and AES. In e-beam evaporation, the deposition temperature of CaRuO3 was the most important since both hi-axial texturing and NiO formation between Ni and CaRuO3 depended on it. Also, the oxygen flow rate had i[n effect on the growth of CaRuO3 on Ni substrates. The optimal conditions of crystal growth and film uniformity were 400$^{\circ}C$, 50 ㎃ and 7 ㎸ when oxygen flow rate was 70∼100sccm In RF magnetron sputtering, CaRuO3 was deposited on Ni substrates with various conditions and annealing temperatures. As a result, the conductivity of CaRuO3 thin films was dependent on CaRuO3 layer thickness and fabrication temperature. We suggested the multi-step deposition, such as two-step deposition with different temperature, to prohibit the NiO formation and to control the hi-axial texture.

• Korean Journal of Materials Research
• /
• v.8 no.12
• /
• pp.1152-1157
• /
• 1998

The PZT films were deposited on the Pt/Ti/$SiO_2$/Si substrates using multi- target DC magnetron reactive sputtering. The perovskite single phase with the composition close to the stoichiometric one, was obtained even at high substrate temperature of $540^{\circ}C$ by 2-step method, which is that PZT film was deposited for a short time at low substrate temperature ($480^{\circ}C$) to promote the nucleation of perovskite phase by reducing the volatility of Pb oxide molecules, followed by the deposition at the elevated temperature to suppress the excess incorporation of Pb component in the PZT film. This two-step method, in combination with the RTA treatment, gives rise to good electrical properties of the deposited PZT films: remanent polarifaion,$18\mu$C/$\textrm{cm}^2$; coercive field, 45kV/cm; leakage current of 10$^{-4}$ A/$\textrm{cm}^2$ at high electric field of -500kV/cm.

• Proceedings of the Korean Vacuum Society Conference
• /
• 2010.02a
• /
• pp.86-86
• /
• 2010

Micro- and nanoscale texturing and control of surface energy have been considered for superhydrophobicity on polymer and silicon. However these surfaces have been reported to be difficult to meet the robustness and transparency requirements for further applications, from self cleaning windows to biochip technology. Here we provided a novel method to fabricate a nearly superhydrophobic soda-lime glass using two-step method. The first step involved wet etching process to fabricate micro-sale patterns on soda-lime glass. The second step involved application of $SiO_x$-incorporated DLC to generate high intrinsic contact angle on the surface using chemical vapor deposition (CVD) process. To investigate the effect of surface roughness, we used both positive and negative micro-scale patterns on soda-limeglass, which is relatively hard for surface texturing in comparison to quartz or Pyrex glasses due to the presence of impurities, but cheaper. For all samples we tested the static wetting angle and transparency before and after 100 cycles of wear test using woolen steel. The surface morphology is observed using optical and scanning electron microscope (SEM). The results shows that negative patterns had a greater wear resistance while the hydrophobicity was best achieved using positive patterns having static contact angle up to 140 deg. with about 80% transparency. The overall experiment shows that positive patterns at etching time of 1 min shows the optimum transparency and hydrophobicity. The optimization of micro-scale pattern to achieve a robust, transparent, superhydrophobic soda-lime glass will be further investigated in the future works.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.39 no.5
• /
• pp.1-7
• /
• 2002

Deep sub-micron bulk CMOS circuits require gate electrode materials such as metal silicide and titanium silicide for gate oxides. Many authors have conducted research to improve the quality of the sub-micron gate oxide. However, few have reported on the electrical quality and reliability of an ultra-thin gate. In this paper, we will recommend a novel shallow trench isolation structure and a two-step TiS $i_2$ formation process to improve the corner metal oxide semiconductor field-effect transistor (MOSFET) for sub-0.1${\mu}{\textrm}{m}$ VLSI devices. Differently from using normal LOCOS technology, deep sub-micron CMOS devices using the novel shallow trench isolation (STI) technology have unique "inverse narrow-channel effects" when the channel width of the device is scaled down. The titanium silicide process has problems because fluorine contamination caused by the gate sidewall etching inhibits the silicide reaction and accelerates agglomeration. To resolve these Problems, we developed a novel two-step deposited silicide process. The key point of this process is the deposition and subsequent removal of titanium before the titanium silicide process. It was found by using focused ion beam transmission electron microscopy that the STI structure improved the narrow channel effect and reduced the junction leakage current and threshold voltage at the edge of the channel. In terms of transistor characteristics, we also obtained a low gate voltage variation and a low trap density, saturation current, some more to be large transconductance at the channel for sub-0.1${\mu}{\textrm}{m}$ VLSI devices.

• Proceedings of the Korean Vacuum Society Conference
• /
• 2014.02a
• /
• pp.361.2-361.2
• /
• 2014

Transition metal dichalcogenides (MoS2, WS2, WSe2, MoSe2, NbS2, NbSe2, etc.) are layered materials that can exhibit semiconducting, metallic and even superconducting behavior. In the bulk form, the semiconducting phases (MoS2, WS2, WSe2, MoSe2) have an indirect band gap. Recently, these layered systems have attracted a great deal of attention mainly due to their complementary electronic properties when compared to other two-dimensional materials, such as graphene (a semimetal) and boron nitride (an insulator). However, these bulk properties could be significantly modified when the system becomes mono-layered; the indirect band gap becomes direct. Such changes in the band structure when reducing the thickness of a WS2 film have important implications for the development of novel applications, such as valleytronics. In this work, we report for the controlled synthesis of large-area (~cm2) single-, bi-, and few-layer WS2 using a two-step process. WOx thin films were deposited onto a Si/SiO2 substrate, and these films were then sulfurized under vacuum in a second step occurring at high temperatures ($750^{\circ}C$). Furthermore, we have developed an efficient route to transfer these WS2 films onto different substrates, using concentrated HF. WS2 films of different thicknesses have been analyzed by optical microscopy, Raman spectroscopy, and high-resolution transmission electron microscopy.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.13 no.9
• /
• pp.729-734
• /
• 2000

Recently, Very Large Scale Integrated (VLSI) circuit & deep-submicron bulk Complementary Metal Oxide Semiconductor(CMOS) devices require gate electrode materials such as metal-silicide, Titanium-silicide for gate oxides. Many previous authors have researched the improvement sub-micron gate oxide quality. However, few have reported on the electrical quality and reliability on the ultra thin gate oxide. In this paper, at first, I recommand a novel shallow trench isolation structure to suppress the corner metal-oxide semiconductor field-effect transistor(MOSFET) inherent to shallow trench isolation for sub 0.1${\mu}{\textrm}{m}$ gate oxide. Different from using normal LOCOS technology deep-submicron CMOS devices using novel Shallow Trench Isolation(STI) technology have a unique"inverse narrow-channel effects"-when the channel width of the devices is scaled down, their threshold voltage is shrunk instead of increased as for the contribution of the channel edge current to the total channel current as the channel width is reduced. Secondly, Titanium silicide process clarified that fluorine contamination caused by the gate sidewall etching inhibits the silicidation reaction and accelerates agglomeration. To overcome these problems, a novel Two-step Deposited silicide(TDS) process has been developed. The key point of this process is the deposition and subsequent removal of titanium before silicidation. Based on the research, It is found that novel STI structure by the SEM, in addition to thermally stable silicide process was achieved. We also obtained the decrease threshold voltage value of the channel edge. resulting in the better improvement of the narrow channel effect. low sheet resistance and stress, and high threshold voltage. Besides, sheet resistance and stress value, rms(root mean square) by AFM were observed. On the electrical characteristics, low leakage current and trap density at the Si/SiO$_2$were confirmed by the high threshold voltage sub 0.1${\mu}{\textrm}{m}$ gate oxide.

• Bulletin of the Korean Chemical Society
• /
• v.33 no.2
• /
• pp.398-402
• /
• 2012

ZnSe/$SiO_2$ coaxial nanowires were synthesized by a two-step process: thermal evaporation of ZnSe powders and sputter-deposition of $SiO_2$. Two different types of nanowires are observed: thin rod-like ones with a few to a few tens of nanometers in diameter and up to a few hundred of micrometers in length and wide belt-like ones with a few micrometers in width. Room-temperature photoluminescence (PL) measurement showed that ZnSe/$SiO_2$ coaxial nanowires had an orange emission band centered at approximately 610 nm. The intensity of the orange emission from the $SiO_2$-sheathed ZnSe nanowires was enhanced significantly by annealing in a reducing atmosphere whereas it was degraded by annealing in an oxidizing atmosphere. The origins of the PL changes by annealing are discussed based on the energy-dispersive X-ray spectroscopy analysis results.