• Journal of Elementary Mathematics Education in Korea
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• v.14 no.1
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• pp.123-134
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• 2010

Recently, mathematics education have been emphasized on developing students' mathematical thinking and problem solving abilities. Accordance with this emphasis, dramatical changes are needed in learning mathematics not merely let alone students solve real-made mathematics problems. The project learning to explore a counterweight activity will have an effects on positive mathematical attitude(to pose problem, to have curiosity) and mathematical thinking(power 10-digit representation, 2-digit number, two representation of 3-digit number, connect exponential number and log situation) which could develop understanding problems and critical thinking.

• International Journal of Fuzzy Logic and Intelligent Systems
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• v.2 no.3
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• pp.237-241
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• 2002

In this paper, we describe how to represent hand witten decimal digits by a sequence of one to five fuzzy sets. Each fuzzy set represents an arc segment of the digit and is a Cartesian product of four fuzzy sets; the first is fur the arc length of the segment, the second is for the arc direction, the third is fur the arc shape, and the fourth is a crisp number indicating whether it has a junction point and if it has an end point of a stroke. We show that an arbitrary pair of these sequences representing two different digits is mutually disjoint. We also show that various forms of a digit written in different styles can be represented by the same sequence of fuzzy sets and hence the deviations due to different writers can be modeled by using these fuzzy sets.

• ETRI Journal
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• v.33 no.5
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• pp.695-703
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• 2011

The number of adders and critical paths in a multiplier block of a multiple constant multiplication based implementation of a finite impulse response (FIR) filter can be minimized through common subexpression elimination (CSE) techniques. A two-bit common subexpression (CS) can be located recursively in a noncanonic sign digit (CSD) representation of the filter coefficients. An efficient algorithm is presented in this paper to improve the elimination of a CS from the multiplier block of an FIR filter so that it can be realized with fewer adders and low logical depth as compared to the existing CSE methods in the literature. Vinod and others claimed the highest reduction in the number of logical operators (LOs) without increasing the logic depth (LD) requirement. Using the design examples given by Vinod and others, we compare the average reduction in LOs and LDs achieved by our algorithm. Our algorithm shows average LO improvements of 30.8%, 5.5%, and 22.5% with a comparative LD requirement over that of Vinod and others for three design examples. Improvement increases as the filter order increases, and for the highest filter order and lowest coefficient width, the LO improvements are 70.3%, 75.3%, and 72.2% for the three design examples.