• Proceedings of the Korean Vacuum Society Conference
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• 2011.08a
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• pp.108-108
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• 2011

Organometallic complexes containing unpaired spins, such as metalloporphyrin or metallophthalocyanine, have extensively studied with increasing interests of their promising model systems in spintronic applications. Additionally, the use of these complexes as an acceptor molecule in chemical sensors has recently received great attentions. In this presentation, we have investigated adsorption of nitric oxide (NO) molecules at Co-porphyrin molecules on Au(111) surfaces with scanning tunneling microscopy and spectroscopy at low temperature. At the location of Co atom in Co-porphyrin molecules, we could observe a Kondo resonance state near Fermi energy in density of states (DOS) before exposing NO molecules and the Kondo resonance state was disappeared after NO exposing because the electronic spin structure of Co-porphyrin were modified by forming a cobalt-NO bonding. Furthermore, we could locally control the chemical reaction of NO dissociations from NO-CoTPP by electron injections via STM probe. After dissociation of NO molecules, the Kondo resonance state was recovered in density of state. With a help of density functional theory (DFT) calculations, we could understand that the modified electronic structures for NO-Co-porphyrin could be occurred by metal-ligand hybridization and the dissociation mechanisms of NO can be explained in terms of the resonant tunneling process via molecular orbitals.

• Proceedings of the Korea Crystallographic Association Conference
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• 2002.11a
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• pp.42-43
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• 2002

반도체 디바이스의 발전은 높은 직접화 및 동작 속도를 추구하고 있으며, 이를 위해서 MOSFET의 scale down시 발생되는 문제를 해결해야만 한다. 특히, Channel이 짧아짐으로써 발생하는 device의 열화현상으로 동작전압의 조절이 어려워 짐을 해결해야만 하며, gate oxide 두께를 줄임으로써 억제할 수 있다고 알려져 왔다. 현재, gate oxide으로 사용되고 있는 SiO2박막은 비정질로써 ～8.7 eV의 높은 band gap과 Si기판 위에서 성장이 용이하며 안정하다는 장점이 있으나, 두께가 1.6 nm 이하로 얇아질 경우 전자의 direct Tunneling에 의한 leakage current 증가와 gate impurity인 Boron의 channel로의 확산, 그리고 poly Si gate의 depletion effect[1,2] 등의 문제점으로 더 이상 사용할 수 없게 된다. 2001년 ITRS에 의하면 ASIC제품의 경우 2004년부터 0.9～l.4 nm 이하의 EOT가 요구된다고 발표하였다. 따라서, gate oxide의 물리적인 두께를 증가시켜 전자의 Tunneling을 억제하는 동시에 유전막에 걸리는 capacitance를 크게 할 수 있다는 측면에서 high-k 재료를 적용하기 위한 연구가 진행되고 있다[3]. High-k 재료로 가능성 있는 절연체들로는 A1₂O₃, Y₂O₃, CeO₂, Ta₂O, TiO₂, HfO₂, ZrO₂,STO 그리고 BST등이 있으며, 이들 재료 중 gate oxide에 적용하기 위해 크게 두 가지 측면에서 고려해야 하는데, 첫째, Si과 열역학적으로 안정하여 후속 열처리 공정에서 계면층 형성을 배제하여야 하며 둘째, 일반적으로 high-k 재료들은 유전상수에 반비례하는 band gap을 갖는 것으로 알려줘 있는데 이 Barrier Height에 지수적으로 의존하는 leakage current때문에 절연체의 band gap이 낮아서는 안 된다는 점이다. 최근 20이상의 유전상수와 ～5 eV 이상의 Band Gap을 가지며 Si기판과 열역학적으로 안정한 ZrO₂[4], HfiO₂[5]가 관심을 끌고 있다. HfO₂은 ～30의 고유전상수, ～5.7 eV의 높은 band gap, 실리콘 기판과의 열역학적 안전성 그리고 poly-Si와 호환성등의 장점으로 최근 많이 연구가 진행되고 있다. 또한, Hf은 SiO₂를 환원시켜 HfO₂가 될 수 있으며, 다른 silicide와 다르게 Hf silicide는 쉽게 산화될 수 있는 점이 보고되고 있다.

• Proceedings of the Korean Vacuum Society Conference
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• 2009.02a
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• pp.107.2-107.2
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• 2009

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 1998.11a
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• pp.165-168
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• 1998

Re-oxidized nitrided oxides which have been investigated as alternative gate oxide for Metal- Oxide -Semiconductor field effect devices were grown by conventional furnace process using pure NH$_3$ and dry $O_2$ gas, and were characterized via a Fowler-Nordheim Tunneling electron injection technique. We studied Ig-Vg characteristics, leakage current, $\Delta$Vg under constant current stress from electrical characteristics point of view and TDDB from reliability point of view of MOS capacitors with SiO$_2$, NO, ONO dielectrics. Also, we studied the effect of stress temperature (25, 50, 75, 100, and 1$25^{\circ}C$). Overall, our results indicate that optimized re-oxidized nitrided oxide shows improved Ig-Vg characteristics, leakage current over the nitrided oxide and SiO$_2$. It has also been shown that re-oxidized nitrided oxide have better TDDB performance than SiO$_2$ while maintaining a similar temperature and electric field dependence. Especially, the Qbd is increased by about 1.5 times.

• Journal of information and communication convergence engineering
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• v.4 no.2
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• pp.84-87
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• 2006

Lateral distributions of locally injected electrons and holes in an oxide-nitride-oxide (ONO) dielectric stack of two different silicon-oxide-nitride-oxide-silicon (SONOS) memory cells are evaluated by single-junction charge pumping technique. Spatial distribution of electrons injected by channel hot electron (CHE) for programming is limited to length of the ONO region in a locally ONO stacked cell, while is spread widely along with channel in a fully ONO stacked cell. Hot-holes generated by band-to-band tunneling for erasing are trapped into the oxide as well as the ONO stack in the locally ONO stacked cell.

• Transactions on Electrical and Electronic Materials
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• v.11 no.4
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• pp.155-165
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• 2010

As a promising candidate to replace the conventional floating gate flash memories, polysilicon-oxide-nitride-oxidesilicon (SONOS)-type nonvolatile semiconductor memories have been investigated widely in the past several years. SONOS-type memories have some advantages over the conventional floating gate flash memories, such as lower operating voltage, excellent endurance and compatibility with standard complementary metal-oxide-semiconductor (CMOS) technology. However, their operating speed and date retention characteristics are still the bottlenecks to limit the applications of SONOS-type memories. Recently, various approaches have been used to make a trade-off between the operating speed and the date retention characteristics. Application of high-k dielectrics to SONOS-type memories is a predominant route. This article provides the state-of-the-art research progress of high-k dielectrics applicable to SONOS-type nonvolatile semiconductor memories. It begins with a short description of working mechanism of SONOS-type memories, and then deals with the materials' requirements of high-k dielectrics used for SONOS-type memories. In the following section, the microstructures of high-k dielectrics used as tunneling layers, charge trapping layers and blocking layers in SONOS-type memories, and their impacts on the memory behaviors are critically reviewed. The improvement of the memory characteristics by using multilayered structures, including multilayered tunneling layer or multilayered charge trapping layer are also discussed. Finally, this review is concluded with our perspectives towards the future researches on the high-k dielectrics applicable to SONOS-type nonvolatile semiconductor memories.

• Current Photovoltaic Research
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• v.12 no.2
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• pp.31-36
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• 2024

Passivating contacts are a promising technology for achieving high efficiency Si solar cells by reducing direct metal/Si contact. Among them, a polysilicon (poly-Si) based passivating contact solar cells achieve high passivation quality through a tunnel oxide (SiO_x) and poly-Si. In poly-Si/SiO_x based solar cells, the passivation quality depends on the amount of dopant in-diffused into the bulk-Si. Therefore, our study fabricated cells by inserting silicon oxide (SiO₂) as a doping barrier before doping and analyzed the barrier effect of SiO₂. In the experiments, p⁺ poly-Si was formed using spin on dopant (SOD) method, and samples ware fabricated by controlling formation conditions such as existence of doping barrier and poly-Si thickness. Completed samples were measured using quasi steady state photoconductance (QSSPC). Based on these results, it was confirmed that possibility of achieving high V_oc by inserting a doping barrier even with thin poly-Si. In conclusion, an improvement in implied V_oc of up to approximately 20 mV was achieved compared to results with thicker poly-Si results.

• KIPS Transactions on Computer and Communication Systems
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• v.5 no.1
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• pp.1-6
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• 2016

This paper focuses on algorithm innovation of NAND Flash Memory for enhancing cell lifetime. During flash memory read/write/erase, the voltage of a specific cell should be a valid voltage level. If not, we cannot read the data correctly. This type of interference/disturbance tends to be serious when program and erase operation will go on. This is because FN tunneling results in tunnel oxide damage due to increased trap site on repetitive high biased state. In order to resolve this problem, we make the cell degradation by reducing the amount of stress in terms of erase cell, resulting in minimizing the cell disturbance on erase verify.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.02a
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• pp.240-240
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• 2010

A multiple alloy metal nano-dots memory using FN tunneling was investigated in order to confirm its structural possibility for future flash memory. In this work, a multiple FePt nano-dots device with a high work function (~5.2 eV) and extremely high dot density (${\sim}\;1.2{\times}10^{13}/cm^2$) was fabricated. Its structural effect for multiple layers was evaluated and compared to one with a single layer in terms of the cell characteristics and reliability. We confirm that MOS capacitor structures with 2-4 multiple FePt nano-dot layers provide a larger threshold voltage window and better retention characteristics. Furthermore, it was also revealed that several process parameters for block oxide and inter-tunnel oxide between the nano-dot layers are very important to improve the efficiency of electron injection into multiple nano-dots. From these results, it is expected that a multiple FePt nano-dots memory using Fowler-Nordheim (FN)-tunneling could be a candidate structure for future flash memory.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.7
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• pp.37-43
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• 2008

In this paper, the dependence of electrical characteristics of Silicon-$Al_2O_3$-Nitride-Oxide-Silicon (SANOS) memory cell transistors and program/erase (P/E) speed, reliability of memory device on interface trap between Si substrate and tunneling oxide and bulk trap in nitride layer were investigated using charge pumping method which has advantage of simple and versatile technique. We analyzed different SANOS memory devices that were fabricated by the identical processing in a single lot except the deposition method of the charge trapping layer, nitride. In the case of P/E speed, it was shown that P/E speed is slower in the SANOS cell transistors with larger capture cross section and interface trap density by charge blocking effect, which is confirmed by simulation results. However, the data retention characteristics show much less dependence on interface trap. The data retention was deteriorated as increasing P/E cycling number but not coincides with interface trap increasing tendency. This result once again confirmed that interface trap independence on data retention. And the result on different program method shows that HCI program method more degraded by locally trapping. So, we know as a result of experiment that analysis the SANOS Flash memory characteristic using charge pumping method reflect the device performance related to interface and bulk trap.