• Journal of IKEEE
• /
• v.10 no.2 s.19
• /
• pp.149-155
• /
• 2006

In this study, the design of low voltage DC-DC converter with low triggering ESD (Electro-Static Discharge) protection circuit was investigated. The purpose of this paper is design optimization for low voltage(2.5V to 5.5V input range) DC-DC converter using CMOS switch. In CMOS switch environment, a dominant loss component is not switching loss but conduction loss at 1.2MHz switching frequency. In this study a constant frequency PWM converter with synchronous rectifier is used. And zener Triggered SCR device to protect the ESD phenomenon was designed. This structure reduces the trigger voltage by making the zener junction between the lateral PNP and base of lateral NPN in SCR structure. The triggering voltage was simulated to 8V.

• Journal of IKEEE
• /
• v.9 no.2 s.17
• /
• pp.161-169
• /
• 2005

This paper presents the new structural Low voltage LVTSCR and TWSCR ESD protection circuit. The proposed ESD protection circuit has lower triggering voltage than conventional circuits. And the LVTSCR has the triggering voltage of 9V, current of 7mA and can pass below 0.8KV (150mA/um). The triggering voltage of the Triple-well SCR measured to 6V and the current is 40mA. By the substrate and gate bias, the triggering voltage is lowered down to $4{\sim}5.5V$.

• Journal of IKEEE
• /
• v.10 no.2 s.19
• /
• pp.141-148
• /
• 2006

In this study, the design of advanced LVDS(Low Voltage Differential Signaling) I/O interface circuit with new structural low triggering ESD (Electro-Static Discharge) protection circuit was investigated. Due to the differential transmission technique and low signal swing range, maximum transmission data ratio of designed LVDS transmitter was simulated to 5Gbps. And Zener Triggered SCR devices to protect the ESD Phenomenon were designed. This structure reduces the trigger voltage by making the zener junction between the lateral PNP and base of lateral NPN in SCR structure. The triggering voltage was simulated to 5.8V. Finally, The high speed I/O interface circuit with the low triggered ESD protection device in one-chip was designed.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
• /
• v.29 no.4
• /
• pp.11-17
• /
• 2015

While most switching devices are based on PN junctions, a single layer can realize a switching device in the case of vanadium dioxide($VO_2$) thin films. In this paper, bidirectional current triggering(switching) is demonstrated in a two-terminal planar device based on a $VO_2$ thin film by illuminating the film with an infrared laser at 1550nm. To begin with, a two-terminal planar device, which had a $30{\mu}m$-wide $VO_2$ conducting layer and an electrode separation of $10{\mu}m$, was fabricated. A specific bias voltage range for stable bidirectional laser triggering was experimentally obtained by measuring the current-voltage characteristics of the fabricated device in a current-controlled mode. Then, by constructing a test circuit composed of the device, a standard resistor, and a DC voltage source, connected in series, the transient response of laser-triggered current and its response time were investigated with a DC bias voltage, included in the above specific bias voltage range, applied to the device. In the test circuit with a DC voltage source of 3.35V and a $10{\Omega}$ resistor, bidirectional laser triggering could be realized with a maximum on-state current of 15mA and a switching contrast of ~78.95.

• Proceedings of the IEEK Conference
• /
• 2005.11a
• /
• pp.805-808
• /
• 2005

In this study, the design of advanced LVDS(Low Voltage Differential Signaling) I/O interface circuit with new structural low triggering ESD(Electro-Static Discharge) protection circuit was investigated. Due to the differential transmission technique and low power consumption at same time. maximum transmission data ratio of designed LVDS transmitter was simulated to 5Gbps, Also, the LIGCSCR(Latch-up Immune Gate Coupled SCR)was designed. It consists of PLVTSCR (P-type Low Voltage Trigger SCR), control NMOS and RC network. The triggering voltage was simulated to 3.6V. And the latch-up characteristics were improved. Finally, we performed the layout high speed I/O interlace circuit with the low triggered ESD protection device in one-chip.

• Proceedings of the Korean Vacuum Society Conference
• /
• 2016.02a
• /
• pp.201.2-201.2
• /
• 2016

The triggered vacuum switch (TVS) is widely used as a high power switch in the field of pulsed power application. TVS can produce current of higher than 100 kA within a microsecond after being triggered. A triggering high voltage pulse generator supplies a high voltage signal to the trigger system to initiate the discharge between a trigger pin and one of main electrode. The trigger system, which consists of a tungsten trigger electrode and cylindrical ceramic insulator around it, is normally installed at the center of main cathode electrode. The discharging characteristics of the trigger system strongly depend on the geometry, electrode material, vacuum pressure and so on. In addition, we especially will focus on the developing a triggering pulse generator, which can vary not only value of voltage but also pulse duration, because its properties gives pivot influences on the TVS discharge. To verify such effects, we made a 3.3 kJ TVS set-up initially. Thus we will discuss some of prominent results from 3.3 kJ TVS system. In parallel we will show on the design of 300 kJ TVS system for the high current in the future.

• Proceedings of the KIEE Conference
• /
• 2002.07c
• /
• pp.1704-1706
• /
• 2002

With increasement of use in electricity energy, quality of electric apparatus has been recognized as important factor in distribution and transmission line. Especially In laboratories, lightning and switching impulse performances of electric apparatus have been carrying out by impulse voltage generator (IVG), simulated into lightning and switching surge circuit. In this paper, we describe triggering system of impulse voltage generator(IVG) for extra high voltage, which has been newly designed.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2004.07a
• /
• pp.397-400
• /
• 2004

The design concept for 8kV light triggering thyristor(LTT) with integrated BOD was discussed here in detail. The trade-off between light triggering input source againsthigh dV/dt limitation has been treated via grooved P-base for gate design. The main application point used for high voltage DC transmission(HVDC) was represented.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
• /
• v.29 no.11
• /
• pp.28-34
• /
• 2015

By incorporating a 966nm near infrared laser, we demonstrated bidirectional current triggering of between 0 and 10mA in a two-terminal planar device based on a highly resistive vanadium dioxide ($VO_2$) thin film grown by a pulsed laser deposition method. A two-terminal planar device, which had an electrode separation of $100{\mu}m$ and a $50{\mu}m-wide$ $VO_2$ conducting layer, was fabricated through ion beam-assisted milling and photolithographic techniques. A bias voltage range for stable bidirectional current triggering was determined by investigating the current-voltage curves of the $VO_2-based$ device in a current-controlled mode. Bidirectional current triggering of up to 10mA was realized by directly illuminating the $VO_2$ film with a focused infrared laser beam, and the transient responses of triggered currents were analyzed when the laser was modulated at various pulse widths and repetition rates. A switching contrast between off- and on-state currents was evaluated as ~3571, and the rising and falling times were measured as ~40 and ~20ms, respectively.

• Proceedings of the IEEK Conference
• /
• 2005.11a
• /
• pp.731-734
• /
• 2005

In this study, the design of advanced LVDS(Low Voltage Differential Signaling) I/O interface circuit with new structural low triggering ESD (Electro-Static Discharge) protection circuit was investigated. Due to the differential transmission technique and low power consumption at the same time. Maximum transmission data ratio of designed LVDS transmitter was simulated to 5Gbps. And Zener Triggered SCR devices to protect the ESD phenomenon were designed. This structure reduces the trigger voltage by making the zener junction between the lateral PNP and base of lateral NPN in SCR structure. The triggering voltage was simulated to 5.8V. Finally, we performed the layout high speed I/O interface circuit with the low triggered ESD protection device in one-chip.