• 조명전기설비학회논문지
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• 제29권4호
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• pp.11-17
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• 2015

While most switching devices are based on PN junctions, a single layer can realize a switching device in the case of vanadium dioxide($VO_2$) thin films. In this paper, bidirectional current triggering(switching) is demonstrated in a two-terminal planar device based on a $VO_2$ thin film by illuminating the film with an infrared laser at 1550nm. To begin with, a two-terminal planar device, which had a $30{\mu}m$-wide $VO_2$ conducting layer and an electrode separation of $10{\mu}m$, was fabricated. A specific bias voltage range for stable bidirectional laser triggering was experimentally obtained by measuring the current-voltage characteristics of the fabricated device in a current-controlled mode. Then, by constructing a test circuit composed of the device, a standard resistor, and a DC voltage source, connected in series, the transient response of laser-triggered current and its response time were investigated with a DC bias voltage, included in the above specific bias voltage range, applied to the device. In the test circuit with a DC voltage source of 3.35V and a $10{\Omega}$ resistor, bidirectional laser triggering could be realized with a maximum on-state current of 15mA and a switching contrast of ~78.95.

• 조명전기설비학회논문지
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• 제29권11호
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• pp.28-34
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• 2015

By incorporating a 966nm near infrared laser, we demonstrated bidirectional current triggering of between 0 and 10mA in a two-terminal planar device based on a highly resistive vanadium dioxide ($VO_2$) thin film grown by a pulsed laser deposition method. A two-terminal planar device, which had an electrode separation of $100{\mu}m$ and a $50{\mu}m-wide$ $VO_2$ conducting layer, was fabricated through ion beam-assisted milling and photolithographic techniques. A bias voltage range for stable bidirectional current triggering was determined by investigating the current-voltage curves of the $VO_2-based$ device in a current-controlled mode. Bidirectional current triggering of up to 10mA was realized by directly illuminating the $VO_2$ film with a focused infrared laser beam, and the transient responses of triggered currents were analyzed when the laser was modulated at various pulse widths and repetition rates. A switching contrast between off- and on-state currents was evaluated as ~3571, and the rising and falling times were measured as ~40 and ~20ms, respectively.

• 전기전자학회논문지
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• 제10권2호통권19호
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• pp.149-155
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• 2006

In this study, the design of low voltage DC-DC converter with low triggering ESD (Electro-Static Discharge) protection circuit was investigated. The purpose of this paper is design optimization for low voltage(2.5V to 5.5V input range) DC-DC converter using CMOS switch. In CMOS switch environment, a dominant loss component is not switching loss but conduction loss at 1.2MHz switching frequency. In this study a constant frequency PWM converter with synchronous rectifier is used. And zener Triggered SCR device to protect the ESD phenomenon was designed. This structure reduces the trigger voltage by making the zener junction between the lateral PNP and base of lateral NPN in SCR structure. The triggering voltage was simulated to 8V.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2005년도 추계종합학술대회
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• pp.805-808
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• 2005

In this study, the design of advanced LVDS(Low Voltage Differential Signaling) I/O interface circuit with new structural low triggering ESD(Electro-Static Discharge) protection circuit was investigated. Due to the differential transmission technique and low power consumption at same time. maximum transmission data ratio of designed LVDS transmitter was simulated to 5Gbps, Also, the LIGCSCR(Latch-up Immune Gate Coupled SCR)was designed. It consists of PLVTSCR (P-type Low Voltage Trigger SCR), control NMOS and RC network. The triggering voltage was simulated to 3.6V. And the latch-up characteristics were improved. Finally, we performed the layout high speed I/O interlace circuit with the low triggered ESD protection device in one-chip.

• 전기전자학회논문지
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• 제10권2호통권19호
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• pp.141-148
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• 2006

In this study, the design of advanced LVDS(Low Voltage Differential Signaling) I/O interface circuit with new structural low triggering ESD (Electro-Static Discharge) protection circuit was investigated. Due to the differential transmission technique and low signal swing range, maximum transmission data ratio of designed LVDS transmitter was simulated to 5Gbps. And Zener Triggered SCR devices to protect the ESD Phenomenon were designed. This structure reduces the trigger voltage by making the zener junction between the lateral PNP and base of lateral NPN in SCR structure. The triggering voltage was simulated to 5.8V. Finally, The high speed I/O interface circuit with the low triggered ESD protection device in one-chip was designed.

• 한국정보전자통신기술학회논문지
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• 제12권2호
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• pp.150-154
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• 2019

In the design of semiconductor integrated circuits, ESD is one of the important issues related to product quality improvement and reliability. In particular, as the process progresses and the thickness of the gate oxide film decreases, ESD is recognized as an important problem of integrated circuit design. Many ESD protection circuits have been studied to solve such ESD problems. In addition, the proposed device can modify the existing SCR structure without adding external circuit to effectively protect the gate oxide of the internal circuit by low trigger voltage, and prevent the undesired latch-up phenomenon in the steady state with high holding voltage. In this paper, SCR-based novel ESD(Electro-Static Discharge) device with the high holding voltage has been proposed. The proposed device has the lower triggering voltage without an external trigger circuitry and the high holding voltage to prevent latch-up phenomenon during the normal condition. Using TCAD simulation results, not only the design factors that influence the holding voltage, but also comparison of conventional ESD protection device(ggNMOS, SCR), are explained. The proposed device was fabricated using 0.35um BCD process and was measured electrical characteristic and robustness. In the result, the proposed device has triggering voltage of 13.1V and holding voltage of 11.4V and HBM 5kV, MM 250V ESD robustness.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2005년도 추계종합학술대회
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• pp.731-734
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• 2005

In this study, the design of advanced LVDS(Low Voltage Differential Signaling) I/O interface circuit with new structural low triggering ESD (Electro-Static Discharge) protection circuit was investigated. Due to the differential transmission technique and low power consumption at the same time. Maximum transmission data ratio of designed LVDS transmitter was simulated to 5Gbps. And Zener Triggered SCR devices to protect the ESD phenomenon were designed. This structure reduces the trigger voltage by making the zener junction between the lateral PNP and base of lateral NPN in SCR structure. The triggering voltage was simulated to 5.8V. Finally, we performed the layout high speed I/O interface circuit with the low triggered ESD protection device in one-chip.

• 한국유체기계학회 논문집
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• 제11권3호
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• pp.50-55
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• 2008

The diverter system is a key component in achieving a high accuracy liquid flow rate standard using a static gravimetric system with a flying start and stop method. The diverter is a moving device used to direct flow alternately along its normal course(by pass) or towards the weighing tank. The time needed for collection into the weighing tank is measured using a timer. So it is important to the diversion period is sufficiently fast and triggering point of timer which is determined the filling time. On this studies show that uncertainty of diverter system for changing diversion speed and triggering point was estimated in accordance with Guide to The Expression of Uncertainty in Measurement(ISO).

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2004년도 하계학술대회 논문집 Vol.5 No.1
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• pp.397-400
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• 2004

The design concept for 8kV light triggering thyristor(LTT) with integrated BOD was discussed here in detail. The trade-off between light triggering input source againsthigh dV/dt limitation has been treated via grooved P-base for gate design. The main application point used for high voltage DC transmission(HVDC) was represented.

• 전기전자학회논문지
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• 제9권2호
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• pp.161-169
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• 2005

본 연구에서는 보다 낮은 트리거 전압을 갖는 새로운 구조의 LVTSCR과 Triple-well SCR ESD 보호회로를 제안 및 설계하여 나노급 회로에 적용하고자 하였다. 제안된 LVTSCR은 약 9V, 약 7mA의 트리거 전압과 전류 및 약 7mA의 홀딩전압 특성을 가지며, 0.8KV(150mA/um) 정도의 ESD 감내 특성을 나타낸다. 한편 Triple-well SCR은 6V, 40mA의 트리거 전압을 가지며, substrate 및 gate 바이어스에 의해 트리거 전압이 4-5.5V 까지 감소하였다.