• 한국멀티미디어학회논문지
• /
• 제17권6호
• /
• pp.725-732
• /
• 2014

The Pancake graph is node symmetric and useful interconnection network in the field of data sorting algorithm. The Half Pancake graph is a new interconnection network that reduces the degree of the Pancake graph by approximately half and improves the network cost of the Pancake graph. In this paper, we analyze topological properties of the Half Pancake graph $HP_n$. Fist, we prove that $HP_n$ has maximally fault tolerance and recursive scalability. In addition, we show that in $HP_n$, there are isomorphic graphs of low-dimensional $HP_n$. Also, we propose that the Bubblesort $B_n$ can be embedded into Half Pancake $HP_n$ with dilation 5, expansion 1. These results mean that various algorithms designed for the Pancake graph and the Bubble sort graph can be executed on $HP_n$ efficiently.

• 전기학회논문지P
• /
• 제58권1호
• /
• pp.38-43
• /
• 2009

Reactors are connected with capacitors to passive filter circuits for reducing harmonics caused by power conversion application. This passive filter frequently gets out of order by voltage and current stress. Especially filter reactor has too much voltage harmonics components, its trouble rate is higher than capacitor. In this paper, we analyzed voltage and current of reactor and capacitor used for passive filter by simulation and measurement. If reactor has a tolerance on variation of reactance value, series resonance frequency is different from originally filter design frequency and parallel resonance can be generated at the close point of the former. Because filter absorbs harmonic component of non-linear load, much of harmonic voltage has been impacted on reactor.

• 한국항공운항학회지
• /
• 제24권1호
• /
• pp.41-46
• /
• 2016

This paper reviews and summarizes overall fatigue substantiation method of aircraft. The fatigue substantiation method has been studied using the related regulation and examples of industry application. And the comparisons of fatigue substantiation procedure between safe-life and damage tolerance design have been performed. Fatigue substantiation methods have wide variability depend on design methodology and type of aircraft such as fixed wing and rotorcraft. In this study, fatigue substantiation methodologies have been reviewed using analysis and test methods.

• Journal of the Optical Society of Korea
• /
• 제15권3호
• /
• pp.244-251
• /
• 2011

We propose a new 2-step phase-shifting digital holographic optical encryption technique and analyze tolerance error for this cipher system. 2-step phase-shifting digital holograms are acquired by moving the PZT mirror with phase step of 0 or ${\pi}$/2 in the reference beam path of the Mach-Zehnder type interferometer. Digital hologram with the encrypted information is Fourier transform hologram and is recorded on CCD camera with 256 gray-level quantized intensities. The decryption performance of binary bit data and image data is analyzed by considering error factors. One of the most important errors is quantization error in detecting the digital hologram intensity on CCD. The more the number of quantization error pixels and the variation of gray-level increase, the more the number of error bits increases for decryption. Computer experiments show the results to be carried out encryption and decryption with the proposed method and the graph to analyze the tolerance of the quantization error in the system.

• 품질경영학회지
• /
• 제42권4호
• /
• pp.607-616
• /
• 2014

Purpose: This paper reviews popular measurement system indices and proposes a procedure for assessing a measurement system using two parameters with intraclass correlation and a factor for process capability. Methods: Gage Repeatability and Reproducibility(GR&R), precision-to-tolerance ratio(PTR), number of distinct categories, producer's and consumer's risks are employed to assess the measurement capabilities and discuss the relationships between measurement system metrics. Results: Two-dimensional plot by two parameters is presented to assess adequacy of the measurement system and process capability. A numerical example and previously studied case study are provided for illustration. Conclusion: The procedure proposed in this paper using two-dimension parameters provides a valuable procedure and helpful guidelines to quality and production managers in assessing the capabilities of a measurement system and choosing the needed actions to be the most benefit.

• 항공우주기술
• /
• 제3권2호
• /
• pp.20-24
• /
• 2004

본 논문에서는 위성용 전자 장비 장착을 위한 인서트의 형태/위치 공차 해석법에 대해 기술한다. 위치 공차를 구하기 위해 순차적 이차 계획법이 사용되었으며, 예제로 다목적 실용위성 2호기 STM(Structure and Thermal Model)의 RDU(Remote Drive Unit)와 OBC(On-Board Computer)의 장착 경우를 해석하였다.

• 한국소음진동공학회:학술대회논문집
• /
• 한국소음진동공학회 2008년도 춘계학술대회논문집
• /
• pp.373-382
• /
• 2008

A method to investigate the design variable tolerance effects on the variances of the response, the characteristics, and the performance of a mechanical system is presented in this paper. The Monte-Carlo method has been conventionally employed to achieve such goals. However, the Monte-Carlo method has some serious drawbacks related to the computation time and the consistent solution convergence. To resolve the drawbacks of the method, a method employing sensitivity information is proposed. Sensitivity equations for a mechanical system are obtained analytically by differentiating the multi-body formulation with respect to a design variable. By using the chain rule along with the sensitivity information, the variances of the response, the characteristics, and the performance of a dynamic system can be calculated.

• 제어로봇시스템학회논문지
• /
• 제20권4호
• /
• pp.443-448
• /
• 2014

Soft errors in memory devices that caused by radiation are the main threat from a reliability point of view. This threat can be commonly overcome with the combination of SEC (Single-Error Correction) codes and scrubbing technique. The interleaving architecture can give memory devices the ability of tolerating these soft errors, especially against multiple-bit soft errors. And the interleaving distance plays a key role in building the tolerance against multiple-bit soft errors. This paper proposes a reliability model of an interleaved memory device which suffers from multiple-bit soft errors and are protected by a combination of SEC code and scrubbing. The proposed model shows how the interleaving distance works to improve the reliability and can be used to make a decision in determining optimal scrubbing technique to meet the demands in reliability.

• 한국초전도ㆍ저온공학회논문지
• /
• 제15권2호
• /
• pp.29-33
• /
• 2013

The understanding of the strain dependence of critical current, $I_c$, in the reversible region is important for the evaluation of the performance of coated conductor (CC) tapes in practical applications. In this study, the stress/strain tolerance of $I_c$ in GdBCO CC tapes with stainless steel substrate stabilized by additional Cu and brass laminate was analyzed quantitatively through $I_c$-strain measurement at 77 K under self-field. The variation in irreversible strain limits of CC tapes by the addition of stabilizing layers was analyzed through the consideration of the pre-strain induced on the GdBCO coating film. The results were then compared with the ones previously reported for GdBCO CC tapes with Hastelloy substrate. As a result, GdBCO CC tapes with stainless steel substrate showed much higher strain tolerance of $I_c$ as compared with those adopting Hastelloy substrate.

• 한국기계가공학회지
• /
• 제16권4호
• /
• pp.119-126
• /
• 2017

High-precision wire is one of the most important components of lead production. However, no studies have been performed on the dimensional tolerance of these wires, and their capabilities have been deduced through trial and error. Therefore, PIANO, a commercial PIDO tool, was used to systematically determine the optimal parameters for stress minimization. The values obtained from the optimum design were modeled and analyzed using LS-Dyna, a finite element analysis program. Maximum stress was reduced by about 10% compared to its initial values, and the wire now satisfies dimensional tolerance ($10{\mu}m$).