• The KIPS Transactions:PartA
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• v.9A no.1
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• pp.61-74
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• 2002

This paper presents a method which synthesizes asynchronous circuits from free-choice Signal Transition Graphs (STGs) with timing constraints. The proposed method synthesizes asynchronous circuits by analyzing: the relations between signal transitions directly from the STGs without generating state graphs. The synthesis procedure decomposes a free-choice STG into deterministic STGs which do not have choice behavior. Then, a timing analysis extracts the timed concurrency and tamed causality relations between any two signal transitions for each deterministic STG. The synthesis procedure synthesizes circuits for each deterministic STG and synthesizes the final circuit by merging the circuits for each deterministic STG. The experimental results show that our method achieves significant reductions in synthesis time for the circuits which have a large state space, and generates circuits that have nearly the same area as compared to previous methods.

• Journal of KIISE:Computer Systems and Theory
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• v.26 no.11
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• pp.1333-1343
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• 1999

경성 실시간 시스템의 태스크들은 논리적으로 올바른 결과를 산출해야 하지만 또한 각자의 시간 제한 조건을 만족하여야 한다. 간격제한 스케줄링은 시간 제한 조건이 시간 간격 제한으로 주어지는 실시간 태스크들을 스케줄하기 위하여 도입되었다. 간격제한 스케줄링에서의 각 태스크들은 시간 간격 제한 조건을 갖는데, 이것은 태스크의 두 연속적인 수행의 종료시간에 대해 제한을 가한다. 다시 말해, 간격제한 스케줄링에서의 각 태스크 수행은 그 태스크의 직전 수행 완료 시간으로부터 발생하는 데드라인을 갖는다. 간격제한 태스크 스케줄링에 관한 많은 연구는 단순화 방법에 기초하고 있다. 그러나, 우리는 이 논문에서 단순화 방법을 사용하지 않고, 정적 우선순위 및 정적 분리 제한 정책을 채용한 새로운 간격제한 태스크 스케줄링 방법을 제안한다. 제안된 정적 할당 방법은 스케줄링 분석 및 구현을 매우 간단히 할 수 있으며, 또한 스케줄러의 실행시간 오버헤드를 줄일 수 있다.Abstract Tasks in hard real-time systems must not only be logically correct but also meet their timing constraints. The distance-constrained scheduling has been introduced to schedule real-time tasks whose timing constraints are characterized by temporal distance constraints. Each task in the distance-constrained scheduling has a temporal distance constraint which imposes restriction on the finishing times of two consecutive executions of the task. Thus, each execution of a task in the distance-constrained scheduling has a deadline relative to the finishing time of the previous execution of the task.Much work on the distance-constrained task scheduling has been based on the reduction technique. In this paper, we propose a new scheme for the distance-constrained task scheduling which does not use the reduction technique but adopts static priority and static separation constraint assignment policy. We show that our static assignment approach can simplify the scheduling analysis and its implementation, and can also reduce the run-time overhead of the scheduler.

• The KIPS Transactions:PartA
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• v.9A no.4
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• pp.459-466
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• 2002

Modern embedded system employs a hybrid architecture which contains a general micro processor and reconfigurable devices such as FPGAS to retain flexibility and to meet timing constraints. It is a hard and important problem for embedded system designers to explore and find a right system configuration, which is known as design space exploration (DSE). With DES, it is possible to predict a final system configuration during the design phase before physical implementation. In this paper, we implement a timing analysis simulator for a DSE on a hybrid embedded system. The simulator, integrating exiting timing analysis tools for hardware and software, is designed by extending Y-chart approach, which allows quantitative performance analysis by varying design parameters. This timing analysis simulator is expected to reduce design time and costs and be used as a core module of a DSE for a hybrid embedded system.

• Journal of the Institute of Electronics and Information Engineers
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• v.54 no.7
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• pp.21-28
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• 2017

Practical models for FPGA architectures which include performance- and/or density-enhancing components such as carry chains, wide function multiplexers, and memory/multiplier blocks are being applied to academic FPGA placement tools which used to rely on simple imaginary models. Previously the techniques such as pre-packing and multi-layer density analysis are proposed to remedy issues related to such practical models, and the wire length is effectively minimized during initial analytic placement. Since timing should be optimized rather than wire length, most previous work takes into account the timing constraints. However, instead of the initial analytic placement, the timing-driven techniques are mostly applied to subsequent steps such as placement legalization and iterative improvement. This paper incorporates the timing driven techniques, which check if the placement meets the timing constraints given in the standard SDC format, and minimize the detected violations, with the existing analytic placer which implements pre-packing and multi-layer density analysis. First of all, a static timing analyzer has been used to check the timing of the wire-length minimized placement results. In order to minimize the detected violations, a function to minimize the largest arrival time at end points is added to the objective function of the analytic placer. Since each clock has a different period, the function is proposed to be evaluated for each clock, and added to the objective function. Since this function can unnecessarily reduce the unviolated paths, a new function which calculates and minimizes the largest negative slack at end points is also proposed, and compared. Since the existing legalization which is non-timing driven is used before the timing analysis, any improvement on timing is entirely due to the functions added to the objective function. The experiments on twelve industrial examples show that the minimum arrival time function improves the worst negative slack by 15% on average whereas the minimum worst negative slack function improves the negative slacks by additional 6% on average.

• The Transactions of the Korea Information Processing Society
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• v.6 no.11
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• pp.3124-3130
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• 1999

A duplex system enhances reliability by tolerating faults through spatial redundancy. Faults can be detected by duplicating identical tasks in pairs of modules. However, this kind of systems cannot even detect the fault if it occurs coincidently due to either malfunctions of common component such as power supply and clock or due to such environmental disruption as EMI. In the paper, we propose a method to reduce those effects of coincident faults in the duplex controller computer. Specifically, a duplex system tolerates coincident faults by using a sophistication sequencing of scheduling technique with certain timing redundancy. In particular when all tasks should be completed in the sense of real-time, the suggested scheduling method works properly to minimize the probability of faulty tasks due to coincident fault without missing the timing constraints.

• Proceedings of the KIEE Conference
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• 2004.11c
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• pp.391-393
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• 2004

For performance and stability of a synchronized system, we need an efficient Clock Tree Synthesis(CTS) methodology to design clock distribution networks. In a system-on-a-chip(SOC) design environment, CTS effectively distributes clock signals from clock sources to synchronized points on layout design. In this paper, we suggest the pre-layout analysis of the clock network including gated clock, multiple clock, and test mode CTS optimization. This analysis can help to avoid design failure with potential CTS problems from logic designers and supply layout constraints so as to get an optimal clock distribution network. Our new design flow including pre-layout CTS analysis and structural violation checking also contributes to reduce design time significantly.

• Journal of Positioning, Navigation, and Timing
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• v.7 no.1
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• pp.1-14
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• 2018

The Global Positioning System (GPS) provides more accurate positioning estimation performance by processing L1 and L2 signals simultaneously through dual frequency signal processing technology at the L-band rather than using only L1 signal. However, if anti-spoofing (AS) mode is run at the GPS, the precision (P) code in L2 signal is encrypted to Y code (or P(Y) code). Thus, dual frequency signal processing can be done only when the effect of P(Y) code is eliminated through the L2 signal processing technology. To do this, a codeless technique or semi-codeless technique that can acquire phase measurement information of L2 signal without information about W code should be employed. In this regard, this paper implements L2 signal processing technology where two typical codeless techniques and four typical semi-codeless techniques of previous studies are applied and compares their performances to discuss the optimal technique selection according to implementation environments and constraints.

• Proceedings of the Korean Society of Computer Information Conference
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• 2018.07a
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• pp.123-126
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• 2018

자율 주행 자동차는 다수의 센서와 ECU 등으로 구성된 분산 시스템이다. 이 시스템은 다양한 시간적 제약사항들을 갖는 자율주행 응용들을 구동하며 각 응용들에 대한 시간적 제약사항 위반을 탐지해야한다. 이러한 분산 시스템에서 응용들 간의 통신을 위해 사용되는 미들웨어들 중 대표적인 것은 DDS이다. DDS는 높은 확장성을 지원하는 발행-구독 통신 모델을 기반으로 하며, 실시간성을 고려한 다양한 QoS 정책들을 제공한다. 하지만 DDS는 자율주행 응용이 요구하는 시간적 제약사항들 중 deadline과 correlation 제약 사항에 대한 위반 여부를 탐지하지 못한다. 본 논문은 DDS 기반 시스템에서 deadline과 correlation 제약 사항 위반 여부를 런타임에서 탐지하는 기법을 제안한다. 본 연구진은 제안된 기법을 DDS의 구현들 중 하나인 Vortex 사의 OpenSplice 기반 시스템에 구현하였다. 실험을 통해 검증한 결과, deadline과 correlation 제약 사항에 대한 위반 여부를 적은 오버헤드와 함께 성공적으로 탐지하였다.

• Proceedings of the IEEK Conference
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• 2007.07a
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• pp.223-224
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• 2007

To develop nuclear measurement system with characteristics including both re-configuration and multi-functions, we proposed a field programmable gate array (FPGA) technique to implement TDC which is more suitable for high energy Physics system. In TDC scheme, the timing resolution is more important than the count rates of channel. In order to manage pico-second resolution TDC, we used the delay components of FPGA, utilized the place and route (P&R) delay difference, and then got two ring oscillators. By setting P&R area constraints, we generated two precise ring oscillators with slightly different frequencies. Finally, we evaluated that the period difference of these two ring oscillators was about 60 pico-seconds, timing resolution of TDC.

• Journal of Positioning, Navigation, and Timing
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• v.13 no.3
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• pp.309-317
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• 2024

Satellite and receiver Inter-Frequency Biases (IFBs) should be estimated or calibrated by pre-defined values for generating precise navigation messages and augmentation data in satellite navigation systems or the augmentation system. In this paper, a Kalman filter is designed and implemented to estimate the ionospheric delay and satellite/receiver IFBs using a regional receiver network. First, an ionospheric model and its filter parameter is defined based on previous studies. Second, a measurement model for estimating the relative satellite/receiver IFBs without any constraints is proposed. Third, a procedure for ensuring the continuity of estimation is proposed in this paper. To verify the performance of the designed filter, six Continuously Operating Reference Stations (CORSs) are selected. Finally, the stability and accuracy of satellite/receiver IFB estimation are analyzed.