• Title/Summary/Keyword: timing analysis

Search Result 1,100, Processing Time 0.029 seconds

Hierarchical Timing Analysis considering Global False Path

  • Sunik Heo;Kim, Juho
    • Proceedings of the IEEK Conference
    • /
    • 2002.07a
    • /
    • pp.235-237
    • /
    • 2002
  • As the integrated circuit technology gets developed, a circuit size of more than thousands of transistors becomes normal. A hierarchical design is unavoidable due to a huge circuit size. It is important how we can consider hierarchical structure in circuit delay analysis. In this paper we present an accurate method to analyze the delay of circuit with hierarchical structure. Adding the notion of global false path to the hierarchical timing analysis performs more accurate timing analysis.

  • PDF

Partitioning and Constraints Generation for the Timing Consistency in the Hierarchical Design Method (계층적 설계 환경에서 일관된 타이밍 분석을 위한 분할 및 제한 조건 생성 기술 개발)

  • Han, Sang-Yong
    • The Transactions of the Korea Information Processing Society
    • /
    • v.7 no.1
    • /
    • pp.215-223
    • /
    • 2000
  • The advancements in technology which have lead to higher and higher levels of integration have required advancements in the methods used in designing VLSI chip. A key to enable a complicated chip design is the use of hierarchy in the design process. Hierarchy organizes the function of a large number of transistors ito a particular, easy-to-manage function. For these reasons, hierarchy has been used in the design process of digital functions for many years. However, there exists differences in a design analysis phase, especially in timing analysis, due to multiple views for the same design. In timing analysis of the hierarchical design, every path is analyzed within partitioned modules independently and the global timing analysis is applied to the whole design considering each module as a single timing component. Therefore, timing results of the hierarchical design could not be same as those of non-hierarchical flat design. In this paper, we formulate the timing problem in the hierarchical design and analyze the possible source of timing differences. We define a new terminology of "consistent result" between different views for the same design. We also propose a new partitioning algorithm to obtain the consistent results. This algorithm helps to enhance the design cycle time.

  • PDF

Extracting the K-most Critical Paths in Multi-corner Multi-mode for Fast Static Timing Analysis

  • Oh, Deok-Keun;Jin, Myeoung-Woo;Kim, Ju-Ho
    • JSTS:Journal of Semiconductor Technology and Science
    • /
    • v.16 no.6
    • /
    • pp.771-780
    • /
    • 2016
  • Detecting a set of longest paths is one of the crucial steps in static timing analysis and optimization. Recently, the process variation during manufacturing affects performance of the circuit design due to nanometer feature size. Measuring the performance of a circuit prior to its fabrication requires a considerable amount of computation time because it requires multi-corner and multi-mode analysis with process variations. An efficient algorithm of detecting the K-most critical paths in multi-corner multi-mode static timing analysis (MCMM STA) is proposed in this paper. The ISCAS'85 benchmark suite using a 32 nm technology is applied to verify the proposed method. The proposed K-most critical paths detection method reduces about 25% of computation time on average.

Design of Timing Analysis Tool for Timing-C Language (Timing-C 언어에서의 시간 분석 도구 설계)

  • 최영준;서진철;이준동;원유헌
    • Proceedings of the Korean Information Science Society Conference
    • /
    • 1999.10a
    • /
    • pp.403-405
    • /
    • 1999
  • 실시간 시스템에서 프로그램의 실행시간을 예측하는 것은 중요한 일이다. 기존의 언어에서는 실행시간은 예측하기에 힘든 요소들이 있다. Timing-C는 이러한 요소를 제거하고 사용자로부터 시간 제약을 입력받을 수 있도록 하였다. Timing-C언어를 이용하여 실시간 프로그램밍을 하기 위해 작성한 프로그램이 시간제약을 준수하고 있는지 알기 위해 시간 분석 도구가 필요하다. 시간 분석 도구는 작성된 프로그램의 실행시간을 제한하여 사용자에게예측된 결과를 알려주는 도구이다. 개발자는 이러한 도구를 이용하여 작성하고 있는 프로그램의 수행시간을 더욱 정확하게 예측할 수 있다.

  • PDF

Timing Analysis Techniques Review for sub-30 nm Circuit Designs

  • Kim, Ju-Ho;Han, Sang-Woo;Jewell, Roy
    • JSTS:Journal of Semiconductor Technology and Science
    • /
    • v.10 no.4
    • /
    • pp.292-299
    • /
    • 2010
  • With scaled technology, timing analysis of circuits becomes more and more difficult. In this paper, we review recently developed circuit simulation techniques created to deal with the cost issues of transistor-level simulations. Various techniques for fast SPICE simulations and Monte Carlo simulations are introduced. Moreover, process and aging variation issues are mentioned, along with promising methodologies.

A Study on Timing Modeling and Response Time Analysis in LIN Based Network System (LIN 프로토콜 시간 모델링 및 메시지 응답 시간 해석에 관한 연구)

  • Youn, Jea-Myoung;Sunwoo, Myoung-Ho;Lee, Woo-Taik
    • Transactions of the Korean Society of Automotive Engineers
    • /
    • v.13 no.6
    • /
    • pp.48-55
    • /
    • 2005
  • In this paper, a mathematical model and a simulation method for the response time analysis of Local Interconnect Network(LIN) based network systems are proposed. Network-induced delays in a network based control system can vary widely according to the transmission time of message and the overhead time of transmission. Therefore, in order to design a distributed control system using LIN network, a method to predict and verify the timing behavior of LIN protocol is required at the network design phase. Furthermore, a simulation environment based on a timing model of LIN protocol is beneficial to predict the timing behavior of LIN. The model equation is formulated with six timing parameters deduced from timing properties of LIN specification. Additionally, LIN conformance test equations to verify LIN device driver are derived with timing constraints of the parameters. The proposed model equation and simulation method are validated with a result that is measured at real LIN based network system.

Statistical Timing Analysis of Partially-Depleted SOI Gates (부분 공핍형 SOI 게이트의 통계적 타이밍 분석)

  • Kim, Kyung-Ki
    • Journal of the Institute of Electronics Engineers of Korea SD
    • /
    • v.44 no.12
    • /
    • pp.31-36
    • /
    • 2007
  • This paper presents a novel statistical characterization for accurate timing analysis in Partially-Depleted Silicon-On-Insulator (PD-SOI) circuits in BSIMSOI3.2 100nm technology. The proposed timing estimate algorithm is implemented in Matlab, Hspice, and C, and it is applied to ISCAS85 benchmarks. The results show that the error is within 5% compared with Monte Carlo simulation results.

A Study on the Timing of Spring Onset over the Republic of Korea Using Ensemble Empirical Mode Decomposition (앙상블 경험적 모드 분해법을 이용한 우리나라 봄 시작일에 관한 연구)

  • Kwon, Jaeil;Choi, Youngeun
    • Journal of the Korean Geographical Society
    • /
    • v.49 no.5
    • /
    • pp.675-689
    • /
    • 2014
  • This study applied Ensemble Empirical Mode Decomposition(EEMD), a new methodology to define the timing of spring onset over the Republic of Korea and to examine its spatio-temporal change. Also this study identified the relationship between spring onet timing and some atmospheric variations, and figured out synoptic factors which affect the timing of spring onset. The averaged spring onset timing for the period of 1974-2011 was 11th, March in Republic of Korea. In general, the spring onset timing was later with higher latitude and altitude regions, and it was later in inland regions than in costal ones. The correlation analysis has been carried out to find out the factors which affect spring onset timing, and global annual mean temperature, Arctic Oscillation(AO), Siberian High had a significant correlation with spring onset timing. The multiple regression analysis was conducted with three indices which were related to spring onset timing, and the model explained 64.7%. As a result of multiple regression analysis, the effect of annual mean temperature was the greatest and that of AO was the second. To find out synoptic factors affecting spring onset timing, the synoptic analysis has been carried out. As a result the intensity of meridional circulation represented as the major factor affect spring onset timing.

  • PDF

A Design and Implementation of a Timing Analysis Simulator for a Design Space Exploration on a Hybrid Embedded System (Hybrid 내장형 시스템의 설계공간탐색을 위한 시간분석 시뮬레이터의 설계 및 구현)

  • Ahn, Seong-Yong;Shim, Jea-Hong;Lee, Jeong-A
    • The KIPS Transactions:PartA
    • /
    • v.9A no.4
    • /
    • pp.459-466
    • /
    • 2002
  • Modern embedded system employs a hybrid architecture which contains a general micro processor and reconfigurable devices such as FPGAS to retain flexibility and to meet timing constraints. It is a hard and important problem for embedded system designers to explore and find a right system configuration, which is known as design space exploration (DSE). With DES, it is possible to predict a final system configuration during the design phase before physical implementation. In this paper, we implement a timing analysis simulator for a DSE on a hybrid embedded system. The simulator, integrating exiting timing analysis tools for hardware and software, is designed by extending Y-chart approach, which allows quantitative performance analysis by varying design parameters. This timing analysis simulator is expected to reduce design time and costs and be used as a core module of a DSE for a hybrid embedded system.

Development and performance analysis of a Miller cycle in a modified using diesel engine

  • Choi, Gyeung-Ho;Poompipatpong, Chedthawut;Koetniyom, Saiprasit;Chung, Yon-Jong;Chang, Yong-Hoon;Han, Sung-Bin
    • Journal of Energy Engineering
    • /
    • v.17 no.4
    • /
    • pp.198-203
    • /
    • 2008
  • The objective of the research was to study the effects of Miller cycle in a modified using diesel engine. The engine was dedicated to natural gas usage by modifying pistons, fuel system and ignition systems. The engine was installed on a dynamometer and attached with various sensors and controllers. Intake valve timing, engine speed, load, injection timing and ignition timing are main parameters. The results of engine performances and emissions are present in form of graphs. Miller Cycle without supercharging can increase brake thermal efficiency and reduce brake specific fuel consumption. The injection timing must be synchronous with valve timing, speed and load to control the performances, emissions and knock margin. Throughout these tested speeds, original camshaft is recommended to obtain high volumetric efficiency. Retard ignition timing can reduce $NO_x$ emissions while maintaining high efficiency.