• Proceedings of the KIEE Conference
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• summer
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• pp.666-670
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• 2004

This paper presents a new approach for determining an accurate incentive levels of Direct Load Control (DLC) program using sequential Monte Carlo Simulation (MCS) techniques. The economic analysis of DLC resources needs to identify the hourly-by-hourly expected energy-not-served resulting from the random outage characteristics of generators as well as to reflect the availability and duration of DLC resources, which results the computational explosion. Therefore, the conventional methods are based on the scenario approaches to reduce the computation time as well as to avoid the complexity of economic studies. In this paper, we have developed a new technique based on the sequential MCS to evaluate the required expected load control amount in each hour and to decide the incentive level satisfying the economic constraints. And also the proposed approach has been considered multi-state as well as two-state of the generating units. In addition, we have applied the variance reduction technique to enhance the efficiency of the simulation. To show the efficiency and effectiveness of the suggested method the numerical studies have been performed for the modified IEEE reliability test system.

• Proceedings of the Korea Society for Simulation Conference
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• 1992.10a
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• pp.5-5
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• 1992

The DEVS(discrete event system specification) formalism describes a discrete event system in a hierarchical, modular form. DEVSIM++ is C++ based general purpose DEVS abstract simulator which can simulate systems to be modeled by the DEVS formalism in a sequential environment. We implement P-DEVSIM++ which is a parallel version of DEVSIM++. In P-DEVSIM++, the external and internal event of models can be processed in parallel. To process in parallel, we introduce a hierarchical distributed simulation technique and some optimistic distributed simulation techniques. But in our algorithm, the rollback of a model is localized itself in contrast to the Time Warp approach. To evaluate its performance, we simulate a single bus multiprocessor architecture system with an external common memory. Simulation result shows that significant speedup is made possible with our algorithm in a parallel environment.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.50 no.1
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• pp.45-50
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• 2001

With increasing complexity of digital logic circuits, fast and accurate verification of functional behaviour becomes most critical bottleneck in meeting time-to-market requirement. This paper presents several techniques for accelerating a cycle-based logic simulation. The acceleration techniques include parallel pattern logic evaluation, circuit size reduction, and the partition of feedback loops in sequential circuits. Among all, the circuit size reduction plays a critical role in maximizing logic simulation speedup by reducing 50% of entire circuit nodes on the average. These techniques are incorporated into a levelized table-driven logic simulation system rather than a compiled-code simulation algorithm. Finally, experimental results are given to demonstrate the effectiveness of the proposed acceleration techniques. Experimental results show more than 27 times performance improvement over single pattern levelized logic simulation.

• Journal of the Korea Society for Simulation
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• v.32 no.3
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• pp.67-74
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• 2023

A semiconductor fabrication facility(FAB) is one of the most capital-intensive and large-scale manufacturing systems which operate under complex and uncertain constraints through hundreds of fabrication steps. To improve fab performance with intuitive scheduling, practitioners have used weighted-sum scheduling. Since the determination of weights in the scheduling significantly affects fab performance, they often rely on simulation-based decision making for obtaining optimal weights. However, a large-scale and high-fidelity simulation generally is time-intensive to evaluate with an exhaustive search. In this study, we investigated three sampling methods (i.e., Optimal latin hypercube sampling(OLHS), Genetic algorithm(GA), and Decision tree based sequential search(DSS)) for the optimization. Our simulation experiments demonstrate that: (1) three methods outperform greedy heuristics in performance metrics; (2) GA and DSS can be promising tools to accelerate the decision-making process.

• Journal of the Korea Society for Simulation
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• v.9 no.1
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• pp.1-9
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• 2000

When a new manufacturing line is constructed, its production capacity can be substantially affected in its design stage. Computer simulation often provides better design by evaluating feasible alternatives. In this paper we study an automobile engine manufacturing line which is under construction. Three alternatives are considered in the design; (1) to use machining tools of longer life; (2) to reassign the buffer space to each sequential processes while maintaining the same total buffer length; and (3) to reduce the machine repair time to 30 minutes using TPM and maintenance team. Simulation results using AutoMod indicates that employing the three alternatives will save about 1.5 million dollars per year.

• Journal of the Korean Institute of Telematics and Electronics
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• v.24 no.3
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• pp.517-526
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• 1987

This paper proposes a new testable design for Zipper CMOS circuits. This design provides an additional feedback loop (called self oscillation loop) whichin the circuit, for testability. The circuit is tested only by observing the oscillation on the loop. The design can be applied to the multistage as well as the single stage, and can detect multiple faults which are undetectable by the conventional testing method. The application and evaluation of test patterns become easy and fault-free responses are not necessary. If the conventional testing method is applied to the sequential Zipper CMOS circuit with the LSSD design technique, it has the serious defect that the initial value may change due to intermediate test patterns and much time taken to apply the necessary test patterns. By using the proposed design, however, the sequential Zipper CMOS circuit with the LSSD design technique can be easily tested without such a defect. Also, the validity of the design is verified by performing the circuit level simulation.

• Proceedings of the KIEE Conference
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• 2000.07d
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• pp.3088-3090
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• 2000

In this paper, we introduce a charge pump PLL architecture which employs precharge phase frequency detector(PFD) and sequential PFD to achieve high frequency operation and fast acquisition. Operation frequency is increased by using precharge PFD when the phase difference is within -${\pi}\;{\sim}\;{\pi}$ and acquisition time is shortened by using sequential PFD and increased charge pump current when the phase difference is larger than |${\pi}$|. SO error detection range of proposed PLL structure is not limited to -${\pi}\;{\sim}\;{\pi}$. By virtue of this multi-phase frequency detector structure, the maximum operating frequency of 423MHz at 2.5V and faster acquisition were achieved by simulation.

• Communications for Statistical Applications and Methods
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• v.23 no.2
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• pp.131-146
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• 2016

In research on behavioral studies, significant attention has been paid to the stage-sequential process for longitudinal data. Latent class profile analysis (LCPA) is an useful method to study sequential patterns of the behavioral development by the two-step identification process: identifying a small number of latent classes at each measurement occasion and two or more homogeneous subgroups in which individuals exhibit a similar sequence of latent class membership over time. Maximum likelihood (ML) estimates for LCPA are easily obtained by expectation-maximization (EM) algorithm, and Bayesian inference can be implemented via Markov chain Monte Carlo (MCMC). However, unusual properties in the likelihood of LCPA can cause difficulties in ML and Bayesian inference as well as estimation in small samples. This article describes and addresses erratic problems that involve conventional ML and Bayesian estimates for LCPA with small samples. We argue that these problems can be alleviated with a small amount of prior input. This study evaluates the performance of likelihood and MCMC-based estimates with the proposed prior in drawing inference over repeated sampling. Our simulation shows that estimates from the proposed methods perform better than those from the conventional ML and Bayesian method.

• Journal of Electrical Engineering and Technology
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• v.7 no.1
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• pp.109-114
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• 2012

In this paper, we utilize training strategy of hidden Markov model (HMM) to use in versatile issues such as classification of time-series sequential data such as electric transient disturbance problem in power system. For this, an automatic means of optimizing HMMs would be highly desirable, but it raises important issues: model interpretation and complexity control. With this in mind, we explore the possibility of using genetic algorithm (GA) and harmony search (HS) algorithm for optimizing the HMM. GA is flexible to allow incorporating other methods, such as Baum-Welch, within their cycle. Furthermore, operators that alter the structure of HMMs can be designed to simple structures. HS algorithm with parameter-setting free technique is proper for optimizing the parameters of HMM. HS algorithm is flexible so as to allow the elimination of requiring tedious parameter assigning efforts. In this paper, a sequential data analysis simulation is illustrated, and the optimized-HMMs are evaluated. The optimized HMM was capable of classifying a sequential data set for testing compared with the normal HMM.

• Journal of Aerospace System Engineering
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• v.11 no.4
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• pp.22-29
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• 2017

A study is performed for the effective detection method of a fault which is occurred during operation in a small turbojet engine with non-linear characteristics used by unmanned air vehicle. For this study the non-linear dynamic model of the engine is derived from transient thermodynamic cycle analysis. Also for inducing real operation conditions the controller is developed associated with unscented Kalman filter to estimate noises. Sequential probability ratio test is introduced as a real time method to detect a fault which is manipulated for simulation as a malfunction of rotational speed sensor contaminated by large amount of noise. The method applied to the fault detection during operation verifies its effectiveness and high feasibility by showing good and definite decision performances of the fault.