• 한국정보통신학회논문지
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• 제11권12호
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• pp.2391-2397
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• 2007

OFDMA의 상향링크 시스템에서 비선형 전력 증폭기와 반송파 주파수 편차의 영향을 고려하여 데이터가 주파수 선택적 Rayleigh 도플러 시변 페이딩 채널을 통하여 전송될 때 비트 오류율을 분석한다. 본 논문에서는 우수한 비트 오류율 특성을 위하여 사용자 수에 따라 요구되는 비선형 증폭기의 최대 출력 전력 대 평균 출력 전력 비(OBO)와 반송파 주파수 편차의 크기를 구하며, 도플러 페이딩의 정도에 따라 결정되는 비트 오류율 특성 열화를 분석한다.

• 재활복지공학회논문지
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• 제7권1호
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• pp.13-19
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• 2013

본 연구는 휠체어 사이클 경사로 주행 시 척수 손상으로 인한 하지마비 장애인의 상체의 근전도 특성을 평가하고자 하였다. 이를 위하여 척수손상 장애인 3명을 대상으로 $0^{\circ}$, $3^{\circ}$, $6^{\circ}$의 경사로에서 휠체어 사이클 주행을 하도록 하였으며, 이때 이두근, 삼두근, 전 삼각근, 상승모근, 광배근, 복직근의 근 활성 최대값과 수축 시간, 수축 개시 종료 시기를 측정 및 분석하였다. 본 연구 결과 휠체어 사이클의 경사로 주행 시 수축 시간과 근 수축 종료시간이 경사도가 증가함에 따라 유의하게 길어지고 지연됐으며, 광배근의 최대 근 활성도는 평지 주행보다 유의하게 증가하였다 (p<0.05). 이와 같은 결과는 휠체어 사이클의 경사로 주행 시 광배근의 과도한 사용을 의미한다.

• 제어로봇시스템학회논문지
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• 제21권7호
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• pp.669-676
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• 2015

In this paper, we described the simulation results of the phase offset performance of a clock in holdover mode which was normally operated in GPS Disciplined Oscillator (GPSDO). In the TIE model, we included the time error term caused by environmental temperature variation because one of the most important parameters of clock phase error is the frequency offset and drift caused by the variation of temperature. For the simulation, we employed Maximum Time Interval Error (MTIE) for the performance evaluation when the frequency offset and drift are estimated by using an Unbiased Finite Impulse Response (UFIR) filter with ladder algorithm. We assumed that the noise in the GPS measurement is white Gaussian with zero mean and 1 ns standard deviation, and temperature linearly varies with a slope of $1{^{\circ}C}$ per hour. From the simulation results, the followings were observed. First, with the estimation error of temperature of less than 3 % and the temperature compensation period of less than 900 seconds, the requirement of CDMA2000 phase synchronization under 10 us could be achieved for more than 40,000 seconds holdover time if we employ an OCXO (Oven Controlled Crystal Oscillator) clock. Second, in order to achieve the requirement of LTE-TDD under 1.5 us for more than 10,000 seconds holdover time, below 3 % estimation error and 500 seconds should be retained if a Rubidium clock is adopted.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2004년도 하계종합학술대회 논문집(1)
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• pp.43-46
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• 2004

In this paper, we present a carrier phase estimation algorithm for LDPC coded systems. LDPC coded system can not achieve the ideal performance if phase offset is introduced by channel. However, the estimation of phase offset is very hard since the operating point of LDPC is very low SNR. To solve this problem, the algorithm using the tentative soft decision value and based on Maximum Likelihood (ML), was proposed in [2]. But this algorithm has problem which works only under constant phase offset. If phase offset is time variant, it has a severe degradation in performance. To solve this problem. we propose two types of estimators. symbol by symbol estimator: Unidirectional estimator (UDE) and hi-directional estimator (BDE), and sub-block estimator (SBE).

• 한국인터넷방송통신학회논문지
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• 제18권3호
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• pp.43-48
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• 2018

파라볼라 오프셋 안테나는 위성 신호 송수신을 위하여 널리 사용된다. 한편, 파라볼라 안테나를 급전하기 위해 혼 안테나를 파라볼라 안테나로부터 이격된 일정 위치에 고정하여야 한다. 하지만 혼 안테나를 고정하기 위한 구조물에 의해 파라볼라 안테나의 방사 패턴에서 부엽 이득이 왜곡되는 문제점이 있다. 따라서 파라볼라 안테나 설계 시 안테나 방사 패턴에서의 부엽 수준을 예측할 수 있어야한다. 기존 시뮬레이션 방법을 이용하면 장시간이 소요되거나 고가의 소프트웨어가 필요하다. 이를 간단하게 해결하기 위해서 광선 추적기법을 이용하여 파라볼라 오프셋 안테나 지오메트리 상에서 계산하여 고각 부엽 각도를 예측한다. 본 논문에서는 광선추적기법을 이용하여 부엽 각도를 계산하고, 계산된 부엽 각도와 시뮬레이션 결과를 비교하여, 예측 방법의 정합성을 보이며 임의의 산란체의 위치 및 각도에 따라 오프셋 파라볼라 안테나의 고각 패턴에 어떠한 영향을 주는지 확인한다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1998년도 추계종합학술대회 논문집
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• pp.413-416
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• 1998

Sensitivity and calibration considerations are most important in the design and implementation of real control systems. Ideally parameter changes due to various causes should not appreciably affect the system's performances. But all the values of physical components of the plants and controllers as well as the relevant environmental conditions change in time, thus the output performance can be deteriorated during the operating span of the system. Naturally the duty of calibration or the prevention of performance deterioration due to excessive component sensitivity should be provided to the control system. In this paper, we propose a digital controller which has the capability of calibration and gain adjustment as well as the execution of control law. Specifically the problems of gain adjustment and offset calibration in the light source and CdS sensor module for position measurement in a flexible link system are considerably resolved. The parameters of measurement module are prone to change due to environmental brightness conditions resulting in poor steady state performance of the overall control system. Thus a proper method is necessary to provide correction to the changed values of gain and offset in the position measurement module. The proposed controller, whenever necessary, measures the open-loop characteristics, andthen calculates the offset and sensor gain correction values based on the prepared standard measurements. It is applied to the control of a flexible link system with the gain and offset calibration porblems in the light sensor module for position to show the applicability.

• 한국정밀공학회지
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• 제25권3호
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• pp.157-164
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• 2008

While developing physical prototype from CAD model, rapid prototyping mainly focuses on two key points reducing time and material consumption. So, we have to change from a traditional solid model to building a hollowed prototype. In this paper, a new method is presented to hollow out solid objects with uniform wall thickness to increase RP efficiency. To achieve uniform wall thickness, it is necessary to generate internal contour by slicing the offset model of an STL model. Due to many difficulties in this method, this paper proposes a new algorithm that computes internal contours computing offset model which is generated from external contour using wall thickness. Proposed method can easily compute the internal contour by slicing the offset surface defined by the sum of circle swept volumes of external contours without actual offset and the circle wept volumes. Internal contour existences are confirmed by using the external point. Presented algorithm uses the 2D geometric algorithm allowing RP implementation more efficient. Various examples have been tested with implementation of the algorithm, and some examples are presented for illustration.

• 한국태양에너지학회 논문집
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• 제37권6호
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• pp.1-12
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• 2017

The DC link of Grid-Connected 3-Phase 3-Level T-type Photovoltaic PCS (PV-PCS) consists of two series connected capacitors for using their neutral voltage. The mismatch between two capacitor characteristics and transient states happened in load change cause the imbalance of neutral voltage. As a result, PV-PCS performance is degraded and the system becomes unstable. In this paper, a mathematical model for analyzing the imbalance of neutral voltage is derived and a compensation method using offset voltage is proposed, where offset voltage adjusts the applying time of P-type and N-type small vectors. The validity of the proposed methods is verified by simulation and experiment.

• 전기학회논문지
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• 제65권6호
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• pp.1108-1114
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• 2016

The cause of failure in the AT feeding system is divided into grounding, short-circuit of feeding circuit and internal faults of the railway substation. Since the fault current is very high, real-time current is detected and the failure must be immediately removed. In this paper, a new DC offset elimination filter that can remove component to decrease in the form of exponential function using low-pass filter was proposed in order to extract the fundamental wave from distorted fault current. In order to confirm the performance of the proposed filter method, AT feeder system was modelled by simulation tool and simulations were performed under various conditions such as fault location, fault resistance and fault voltage phase angle in case of trolley-rail short-circuit fault. When applying the proposed DC-offset removal method, it can be seen that the phase delay and gain error did not appear.

• 한국정밀공학회지
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• 제31권6호
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• pp.497-504
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• 2014

The digital signage display is actively researched as the next generation of large FPD. To commercialize those digital signage display, the manufacturing cost must be downed with printing method instead of conventional photolithography. Here, we demonstrate a reverse offset printed TFT electrodes for the digital signage display. For the fabricated source/drain and gate electrode, we used Ag ink, silicone blanket, Clich$\acute{e}$ and reverse offset printer. We printed uniform TFT electrode patterns with narrow line width(10 ${\mu}m$ range) and thin thickness(nm range). In the end the printing source/drain and gate electrode are successfully achieved by optimization of experimental conditions such as Clich$\acute{e}$ surface treatment, ink coating process, delay time, off/set process and curing temperature. Also, we checked that the printing align accuracy was within 5 ${\mu}m$.