• Journal of IKEEE
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• v.23 no.3
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• pp.858-864
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• 2019

A clock system is proposed to eliminate data loss due to frequency difference between sensor nodes in a sensor utility network. The proposed clock system for each sensor node consists of a bust clock-data recovery (CDR) circuit, a digital phase-locked loop outputting a 32-phase clock, and a digital frequency synthesizer using a programmable open-loop fractional divider. A CMOS oscillator using an active inductor is used instead of a burst CDR circuit for the first sensor node. The proposed clock system is designed by using a 65 nm CMOS process with a 1.2 V supply voltage. When the frequency error between the sensor nodes is 1%, the proposed burst CDR has a time jitter of only 4.95 ns with a frequency multiplied by 64 for a data rate of 5 Mbps as the reference clock. Furthermore, the frequency change of the designed digital frequency synthesizer is performed within one period of the output clock in the frequency range of 100 kHz to 320 MHz.

• Journal of Positioning, Navigation, and Timing
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• v.13 no.1
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• pp.111-115
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• 2024

This study builds a machine learning model optimized for clocks among various techniques in the field of artificial intelligence and applies it to clock stabilization or synchronization technology based on atomic clock noise characteristics. In addition, the possibility of providing stable source clock data is confirmed through the characteristics of machine learning predicted values during holdover of atomic clocks. The proposed machine learning model is evaluated by comparing its performance with the AutoRegressive Integrated Moving Average (ARIMA) model, an existing statistical clock prediction model. From the results of the analysis, the prediction model proposed in this study (MSE: 9.47476) has a lower MSE value than the ARIMA model (MSE: 221.2622), which means that it provides more accurate predictions. The prediction accuracy is based on understanding the complex nature of data that changes over time and how well the model reflects this. The application of a machine learning prediction model can be seen as a way to overcome the limitations of the statistical-based ARIMA model in time series prediction and achieve improved prediction performance.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.38 no.1
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• pp.58-63
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• 2010

In this paper, we propose a simple technique for the detection of a frequency jump in the GPS clock behavior. GPS satellite atomic clocks have characteristics of a second order polynomial in the long term and a non-periodic frequency drift in the short term, showing a sudden frequency jump occasionally. As satellite clock anomalies influence on GPS measurements, it requires to develop a real time technique for the detection of the clock anomaly on the real-time GPS precise point positioning. The proposed technique is based on Teager energy which is mainly used in the field of various signal processing for the detection of a specific signal or symptom. Therefore, we employed the Teager energy for the detection of the jump phenomenon of GPS satellite atomic clocks, and it showed that the proposed clock anomaly detection strategy outperforms a conventional detection methodology.

• ETRI Journal
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• v.36 no.2
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• pp.321-324
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• 2014

This letter describes a two-phase clock oxide thin-film transistor shift register that executes a robust operation over a wide threshold voltage range and clock coupling noises. The proposed circuit employs an additional Q generation block to avoid the clock coupling noise effects. A SMART-SPICE simulation shows that the stable shift register operation is established for the clock coupling noises and the threshold voltage variation from -4 V to 5 V at a line time of $5{\mu}s$. The magnitude of coupling noises on the Q(15) node and Qb(15) node of the 15th stage is respectively -12.6 dB and -26.1 dB at 100 kHz in the proposed circuit, compared to 6.8 dB and 10.9 dB in a conventional one. In addition, the estimated power consumption is 1.74 mW for the proposed 16-stage shift registers at $V_{TH}=-1.56V$, compared to 11.5 mW for the conventional circuits.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.10
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• pp.63-68
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• 2004

A high-resolution synchronous mirror delay (SMD) is proposed in order to reduce the clock skew between the external clock and the infernal clock of a chip. The proposed SMD reduces the clock skew in two steps. Coarse locking is achieved by the SMD. Fine locking is achieved by the successive approximation register-controlled DLL. The total locking time is 10 clock cycles. Simulation results show that the proposed SMD operates with 50psec clock skew at 182MHz and consumes 17.5mW at 3.3V supply voltage in a 0.35 um 1-poly 4-metal CMOS technology.

• Journal of information and communication convergence engineering
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• v.3 no.3
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• pp.142-145
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• 2005

In this paper, a new programmable DLL (delay locked loop) based clock synthesizer is proposed. DLL has several inherent advantages, such as no phase accumulation error, fast locking and easy integration of the loop filter. This paper proposes a new programmable DLL that includes a PFD(phase frequency detector), a LSI(lock status indicator), and a VCDL(voltage controlled delay line) to generate multiple clocks. It can generate clocks from 3 to 9 times of input clock with $2{\mu}s$ locking time. The proposed DLL operating in the frequency range of 300MHZ-900MHz is verified by the HSPICE simulation with a $0.35{\mu}m$ CMOS process.

• Journal of Positioning, Navigation, and Timing
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• v.5 no.3
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• pp.137-144
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• 2016

In this paper, the performance of ranging measurement, which is generated using two receiver clock offsets in one receiver, was analyzed. A spoofer transmits a counterfeited spoofing signal which is similar to the GPS signal with hostile purposes, so the same tracking technique can be applied to the spoofing signal. The multi-correlator can generate two receiver clock offsets in one receiver. The difference between these two clock offsets consists of the path length from the spoofer to the receiver and the delay of spoofer system. Thus, in this paper, the ranging measurement was evaluated by the spoofer localization performance based on the time-of-arrival (TOA) technique. The results of simulation and real-world experiments show that the position and the system clock offset of the spoofer could be estimated successfully.

• Journal of Photoscience
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• v.9 no.2
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• pp.243-245
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• 2002

Pigment-dispersing factor (PDF) is an octadecapeptide distributed in the optic lobe and the brain in a variety of insect species. There are lines of evidence suggesting possible involvement of PDF in the insect circadian system. However, its physiological roles in the circadian time keeping mechanism have not been clearly defined. In this study, we have examined the phase shifting effects of Gryllus-PDF on the circadian locomotor rhythm in the cricket Gryllus bimaculatus of which circadian clock is located in the optic lobe. Phase shifts in the circadian activity rhythm were measured following microinjection of 22nl of vehicle (Ringer's solution) or O.lmM PDF into the optic lobe through the compound eye at various circadian times. The results showed that PDF induced phase shifts of the circadian clock in a phase-dependent manner, suggesting that it may play a role as an input signal for the circadian clock.

• Proceedings of the Korean Information Science Society Conference
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• 1998.10a
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• pp.243-245
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• 1998

미래의 셀룰라 이동통신망은 멀티미디어 데이터 서빗를 제공하기 위해서 높은 대역폭이 필요하기 때문에 셀의 크기가 수십 미터 내오인 피코 실(pico cell)로 구성되는 피코 셀 망이 될 것이다. 이와 같은 피코 셀룰라 망에서는 이동통신자의 우치 변화에 따른 handoff 처리 회수가 상대적으로 증가하므로, handoff 처리로 인한 망부하가 늘어났고, handoff처리 지연으로 인하여 사용자는 중단없는 연결서비스 (seamless connection service)를 받지 못할 수도 있다. 본 논문은 VT-CSMA방식을 응용한 기법을 새로운 handoff방식으로 제안한다. 이 기법은 handoff에서 사용하고 delay time virtual clock 과 real clock 의 2개의 clock을 갖도록 함으로써, 빠른 속도로 이동하는 호는 느린 속도로 이동하는 호보다 상대적으로 짧은 시간 내에 handoff가 처리 되도록 한다. 모의 실험 결과는 VT-CSMA기법을 응용한 새로운 방식이 기존 CDMA 방식에서 drop되는 호를 많이 줄이는 효과가 있음을 보인다.

• Proceedings of the Korean Society of Agricultural Engineers Conference
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• 1998.10a
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• pp.224-229
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• 1998

This study was conducted to develop the simple and convenient irrigation control model which can maintain the appropriate rates of irrigation and drainage of nutrient solution according to the environmental conditions and growth stages in soilless culture of cucumber. In order to obtain fundamental data for development of the model, investigation of the actual state of soilless culture practices was carried out. Most irrigation systems of soilless culture were controlled by the time clock. Evapotranspiration of cucumber in soilless culture was investigated and correlations with environmental conditions were analyzed, and its prediction model was developed. A irrigation control model based on the time clock control and there were considered seasons, weather conditions, and growth stages was developed. Applicability of the model was tested by simulation. Drainage rates of irrigation system controlled by conventional time clock, integrated solar radiation, and the developed model were 61%, 20%, and 32%, respectively in cucumber perlite culture.