• The KIPS Transactions:PartA
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• v.16A no.2
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• pp.79-88
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• 2009

In boundary scan architecture, test stimuli are shifted in one at a time and applied to the on-chip system logic. The test results are captured into the BSR and are examined by subsequent shifting. In this paper, we developed a continuous capture test architecture and test procedure using TPG based on boundary scan is used to performance test. In this architecture, test patterns of TPG are applied to CUT with system clock rate, and response of CUT is continuously captured by CBSR(Continuous Capture Boundary Scan Register) at the same rate and the captured results is shifted to TDO at the same rate. The suggested a continuous capture test architecture and test procedure is simulated by Altera Max+Plus 10.0. The simulation results shows the accurate operation and effectiveness of the proposed test architecture and procedure.

• Journal of the Institute of Convergence Signal Processing
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• v.12 no.2
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• pp.107-112
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• 2011

Several developed countries have been developing their own satellite navigation systems, such as Europe's Galileo, China's BEIDOU, and Japan's QZSS, to cope with clock errors and signal vulnerabilities of GPS. In addition, modernization of Loran, eLoran, for GPS backup has been conducted. In Korea, a dependent navigation system has been required and for GPS backup, the need for utilization of time synchronization infrastructure through the modernization of Loran has been raised. Loran signal uses 100Khz groundwave. A significant factor limiting the ranging accuracy of the Loran signal is the ASF arising from the fact that the groundwave signal is likely to propagate over paths of varying conductivity and topography. Thus, an ASF compensation method is very important for Loran and eLoran navigation. This paper introduces the propagation delay model and then compares and analyzes the estimations from the propagation delay model and measured ASFs.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2016.10a
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• pp.602-604
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• 2016

In this paper, we propose that it can control the interior lighting, LED and alarm clocks based on Bluetooth. The proposed 'Bluetooth based LED Alarm Lamp'may be an ON / OFF by using a Bluetooth module, by the light sensor and voltage transformers were designed to adjust the ON / OFF and light intensity. Also 7-segment display the clock, it was used a piezo-buzzer that designed to ring an alarm in time. And to decrease the voltage by using the touch sensor can adjust the light brightness. It was also added the ability to align the alarm. This piece (Bluetooth based LED Alarm Lamp) can provide a comfortable environment inside the room of a resident if the environment is dark when voltage is maintained to be ON automatic system. And designed with emphasis being able to improve the quality of sleep due to weak light.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.30 no.6
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• pp.1247-1254
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• 2020

With the advent of the smart home era, equipment that provides confidentiality or performs authentication exists in various places in real life. Accordingly security against physical attacks is required for encryption equipment and authentication equipment. In particular, fault injection attack that artificially inject a fault from the outside to recover a secret key or bypass an authentication process is one of the very threatening attack methods. Fault sources used in fault injection attacks include lasers, electromagnetic, voltage glitches, and clock glitches. Fault injection attacks are classified into single fault injection attacks and multiple fault injection attacks according to the number of faults injected. Existing multiple fault injection systems generally use a single fault source. The system configured to inject a single source of fault multiple times has disadvantages that there is a physical delay time and additional equipment is required. In this paper, we propose a multiple fault injection system using heterogeneous fault sources. In addition, to show the effectiveness of the proposed system, the results of a multiple fault injection attack against Riscure's Piñata board are shown.

• Journal of Korean Society of Occupational and Environmental Hygiene
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• v.32 no.3
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• pp.221-230
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• 2022

Objectives: The aim of this study is to evaluate the association between shiftwork and skeletal muscle mass index in a single university health check-up. Methods: We used data from 98,227 workers who answered in a special interview on health check-up at a local university hospital from 2014 to 2020. Pearson correlation analysis was conducted for comparing the association between skeletal muscle mass index and demographic and hematological variables in shiftwork and non-shiftwork groups. Mixed linear model analysis after controlling demographic and hematological variables was used to analyze the difference of skeletal muscle mass index between groups at every visit for seven years. Results: In linear regression analysis, the variables most significantly correlated with skeletal muscle index in both groups were shiftwork(p=0.049), BMI(p<0.001), hypertension(p=0.024), platelet(p<0.001), total protein (p<0.001), AST(p=0.028), ALT(p=0.003), ALP(p<0.001), total cholesterol(p=0.002), triglyceride(p=0.019), BUN (p=0.001), creatinine(p<0.001), and uric acid(p=0.002). After the adjustment for demographic and hematologic variables, the skeletal muscle mass index at every visit was decreased both in the shiftwork group and non-shiftwork group. The slope of the shiftwork group was -0.240 and non-shiftwork group -0.149, showing a significant difference (p<0.001). Conclusions: In the shiftwork group, the skeletal muscle mass index showed a tendency to decrease markedly over time compared to the non-shiftwork group. It is presumed that shift workers' skeletal muscle health was adversely affected by changes in the biological clock due to changes in wake-up and sleep patterns, and changes in food intake.

• Asia-pacific Journal of Multimedia Services Convergent with Art, Humanities, and Sociology
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• v.7 no.3
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• pp.301-310
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• 2017

Quantum-dot cellular automata(QCA) is an alternative technology for implementing various computation, high performance, and low power consumption digital circuits at nano scale. In this paper, we propose a new universal gate in QCA. By using the universal gate, we propose a novel XOR gate which is reduced time/hardware complexity. The universal gate can be used to construct all other basic logic gates. Meanwhile, the proposed universal gate is designed by basic cells and a rotated cell. The rotated cell of the proposed universal gate is located at the central of 3-input majority gate structure. In this paper, we propose an XOR gate using three universal gates, although more than five 3-input majority gates are used to design an XOR gate using the 3-input majority gate. The proposed XOR gate is superior to the conventional XOR gate in terms of the total area and the consumed clock because the number of gates are reduced.

• International Journal of Computer Science & Network Security
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• v.23 no.7
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• pp.1-8
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• 2023

An Orthogonal Frequency Division Multiplexing (OFDM) based wireless communication system has drawn wide attention for its high transmission rate and high spectrum efficiency in not only radio but also Underwater Acoustic (UWA) applications. Because of the narrow sub-carrier spacing of OFDM, orthogonality between sub-carriers is easily affected by Doppler effect caused by the movement of transmitter or receiver. Previously, Doppler compensation signal processing algorithm for Desired propagation path was proposed. However, other Doppler shifts caused by delayed Undesired signal arriving from different directions cannot be perfectly compensated. Then Receiver Bit Error Rate (BER) is degraded by Inter-Carrier-Interference (ICI) caused in the case of Multi-path Doppler channel. To mitigate the ICI effect, a modified Delay and Doppler Profiler (mDDP), which estimates not only attenuation, relative delay and Doppler shift but also sampling clock shift of each multi-path component, is proposed. Based on the outputs of mDDP, an ICI canceling multi-tap equalizer is also proposed. Computer simulated performances of one-tap equalizer with the conventional Time domain linear interpolated Channel Transfer Function (CTF) estimator, multi-tap equalizer based on mDDP are compared. According to the simulation results, BER improvement has been observed. Especially, in the condition of 16QAM modulation, transmitting vessel speed of 6m/s, two-path multipath channel with direct path and ocean surface reflection path; more than one order of magnitude BER reduction has been observed at CNR=30dB.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.8C
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• pp.1113-1124
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• 2004

In this paper, we proposed a hardware(H/W) structure which can compress and recontruct the input image in real time operation and implemented it into a FPGA platform using VHDL(VHSIC Hardware Description Language). All the image processing element to process both compression and reconstruction in a FPGA were considered each of them was mapped into H/W with the efficient structure for FPGA. We used the DWT(discrete wavelet transform) which transforms the data from spatial domain to the frequency domain, because use considered the motion JPEG2000 as the application. The implemented H/W is separated to both the data path part and the control part. The data path part consisted of the image processing blocks and the data processing blocks. The image processing blocks consisted of the DWT Kernel fur the filtering by DWT, Quantizer/Huffman Encoder, Inverse Adder/Buffer for adding the low frequency coefficient to the high frequency one in the inverse DWT operation, and Huffman Decoder. Also there existed the interface blocks for communicating with the external application environments and the timing blocks for buffering between the internal blocks The global operations of the designed H/W are the image compression and the reconstruction, and it is operated by the unit of a field synchronized with the A/D converter. The implemented H/W used the 69%(16980) LAB(Logic Array Block) and 9%(28352) ESB(Embedded System Block) in the APEX20KC EP20K600CB652-7 FPGA chip of ALTERA, and stably operated in the 70MHz clock frequency. So we verified the real time operation of 60 fields/sec(30 frames/sec).

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.6
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• pp.13-21
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• 2010

A energy efficient $V_{pp}$ generator using a variable pumping frequency for mobile DRAM is presented in this paper. The proposed $V_{pp}$ generator exploits 3 stages of a cross-coupled charge pump for energy efficiency. Instead of using a fixed pumping frequency in the conventional $V_{pp}$ generator, our proposed $V_{pp}$ generator adopts a voltage-controlled oscillator and uses variable frequencies to reduce the ramp-up time. As a result, our $V_{pp}$ generator generates 3.0 V output voltage with 24.0-${\mu}s$ ramp-up time at 2 mA current load and 1 nF capacitor load with 1.2 V supply voltage. Experimental results show that the proposed $V_{pp}$ generator consumes around 26% less energy (1573 nJ $\rightarrow$ 1162 nJ) and reduces 29% less ramp-up time (33.7-${\mu}s$ $\rightarrow$ 24.0-${\mu}s$) compared to the conventional approach.

• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.12
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• pp.201-208
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• 2012

In this paper, the hardware design of rate control for real-time video encoded is proposed. In the proposed method, a quadratic rate distortion model with high-computational complexity is not used when quantization parameter values are being decided. Instead, for low-computational complexity, average complexity weight values of frames are used to calculate QP. For high speed and low computational prediction, the MAD is predicted based on the coded basic unit, using spacial and temporal correlation in sequences. The rate control is designed with the hardware for fast QP decision. In the proposed method, a quadratic rate distortion model with high-computational complexity is not used when quantization parameter values are being decided. Instead, for low-computational complexity, average complexity weight values of frames are used to calculate QP. In addition, the rate control is designed with the hardware for fast QP decision. The execution cycle and gate count of the proposed architecture were reduced about 65% and 85% respectively compared with those of previous architecture. The proposed RC was implemented using Verilog HDL and synthesized with UMC $0.18{\mu}m$ standard cell library. The synthesis result shows that the gate count of the architecture is about 19.1k with 108MHz clock frequency.