• 정보처리학회논문지C
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• 제19C권3호
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• pp.209-214
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• 2012

시각 동기화는 무선 센서 네트워크에서 시각 정보가 활용되는 응용(예, 감시, 추적, 데이터 융합, 스케쥴링)에 있어서 중요하다. 무선 센서 네트워크에서의 시각 동기화는 기존의 유선 인터넷 망이나 다른 무선 통신망과도 다른 요구 사항을 만족해야 하는데, 이는 무선 센서 네트워크가 제한된 자원을 가지고 있기 때문이며, 그 중 특히 전력 소모가 가장 중요한 요소이다. 이 논문은 무선 센서 네트워크에서 동작하는 새로운 시각 동기화 방안에 관한 것으로 메시지 통신 부하를 줄여 결과적으로 전력 소모를 줄일 수 있다. 시뮬레이션 시험을 통해서 제안한 시각 동기화 방안이 기존의 방안보다 에너지 소모가 적으며 정확도가 향상되었음을 보인다.

• 전기전자학회논문지
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• 제8권2호
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• pp.166-171
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• 2004

본 논문은 두 신호의 시간 차이를 디지털 신호로 변환하는 시간디지털변환기(Time to Digital Converter) 변환기에 대해서 서술하였다. 시간 차이를 측정하는 방법에는 여러 가지가 있으나 변환시간이나 저해상도의 단점을 가지고 있으며 또한 복잡한 구조를 가지는 문제점이 있다. 그러나 본 논문에서 제안한 시간디지털변환기회로는 고속 디지털 샘플러를 사용함으로써 단순한 구조로 높은 해상도(25ps)를 실현할 수 있었다. 입력신호가 시간디지털변환기의 입력으로 들어오면 샘플러가 신호를 검출해내고 레지스터에 의해 처리된 후 코딩블럭에 의해서 코딩되게 된다. 또한 25ps의 해상도를 얻기 위해서 본 논문에서는 다중위상클록발생기를 구현하였다.

• KSII Transactions on Internet and Information Systems (TIIS)
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• 제13권8호
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• pp.3880-3899
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• 2019

Distributive desynchronization algorithms based on pulse-coupled oscillator (PCO) models have been proposed for achieving collision-free wireless transmissions. These algorithms do not depend on a global clock or infrastructure overheads. Moreover, they gradually converge to fair time-division multiple access (TDMA) scheduling by broadcasting a periodic pulse signal (called a 'firing') and adjusting the next firing time based on firings from other nodes. The time required to achieve constant spacing between phase neighbors is estimated in a closed form or via stochastic modeling. However, because these algorithms cannot guarantee the completion of desynchronization in a short and bounded timeframe, they are not practical. Motivated by the limitations of these methods, we propose a practical solution called PD-DESYNC that provides a short and deterministic convergence time using a flag firing to indicate the beginning of a cycle. We demonstrate that the proposed method guarantees the completion of desynchronization within three cycles, regardless of the number of nodes. Through extensive simulations and experiments, we confirm that PD-DESYNC not only outperforms other algorithms in terms of convergence time but also is a practical solution.

• 전기학회논문지
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• 제57권6호
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• pp.1081-1086
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• 2008

This paper presents the $3^{rd}$ 4bit sigma delta modulator with the block and timing diagrams of DWA(Data Weighted Averaging) to optimize a operating time. In the modulator, the proposed DWA structure has a stable operation and timing margin so as to remove three latches and another clock. Because the modulator with proposed DWA structure improve timing margin about 23%. It can increase sampling frequency up to 244MHz. Through the MATLAB modeling, the optimized coefficients are obtained to design the modulator. The fully differential SC integrators, DAC, switch, quantizer, and DWA are designed by considering the nonideal characteristics. The designed $3^{rd}$ order 4bit modulator has a power consumption of 40mW and SNR(signal to noise ratio) of 77.2dB under 1.2V supply and 64MHz sampling frequency.

• ETRI Journal
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• 제32권6호
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• pp.911-920
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• 2010

This paper presents a method of designing hybrid analog/asymmetrical square-root (SR) FIR filters. In addition to the conventional frequency domain constraints, the proposed method considers time-domain constraints as well, including the inter-symbol interference (ISI) and the opening of the eye pattern at the receiver output. This paper also reviews a systematic way to find the discrete-time equivalence of analog parts in a band-limited digital communication system. Thus, a phase equalizer can be easily realized to compensate for the nonlinear phase responses of the analog components. With the hybrid analog/SR FIR filter co-design, examples show that using the proposed method can result in a more robust ISI performance in the presence of the receiver clock jitter.

• ETRI Journal
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• 제30권1호
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• pp.129-140
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• 2008

In this paper, we propose a novel ant colony optimization (ACO)-based test scheduling method for testing network-on-chip (NoC)-based systems-on-chip (SoCs), on the assumption that the test platform, including specific methods and configurations such as test packet routing, generation, and absorption, is installed. The ACO metaheuristic model, inspired by the ant's foraging behavior, can autonomously find better results by exploring more solution space. The proposed method efficiently combines the rectangle packing method with ACO and improves the scheduling results by dynamically choosing the test-access-mechanism widths for cores and changing the testing orders. The power dissipation and variable test clock mode are also considered. Experimental results using ITC'02 benchmark circuits show that the proposed algorithm can efficiently reduce overall test time. Moreover, the computation time of the algorithm is less than a few seconds in most cases.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2004년도 하계종합학술대회 논문집(1)
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• pp.183-186
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• 2004

The proposed system in this paper utilizes the SIP and self-defined control protocol to provide global wireless communication over the data link of Orbcomm system. Main processor board connected to Orbcomm communication subscriber is designed to interface with digital I/O and AD/DA convertor for various application of control and .measurement. Hardware system implemented in this paper also includes the function of real-time clock and position report using GPS receiver The experimental result of the proposed global wireless communication system is evaluated via real-time experiments, and we have confirmed it works well according to the protocol designed in this paper.

• 한국국방경영분석학회지
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• 제17권2호
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• pp.123-134
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• 1991

one of the problems the users of DPS-6/45 used to face in the course of having access to work stations was that a telephone call has to be made manually every time to have receiver's modem on or off, and naturally it meant the waste of manpower as well as of time. A program has been worked out to automatically operate and control. utilizing the system clock within the main computer (DPS-6/45), the on/off switch on the modems. It has resulted in; 1) promotion in operability of the main computer, DPS-6/45 2) prevention of unnecessary telephone calls 3) curtailment of expenditure and manpower

• 대한의용생체공학회:의공학회지
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• 제6권2호
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• pp.13-14
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• 1985

We have developed a microprogramir!able signal processor for real-time ultrasonic signal processing. Processing speed was increased by the parallelism in horizontal microprogram using 104bits microcode and the Pipelined architecture. Control unit of the signal processor was designed by microprogrammed architec- ture and writable control store (WCS) which was interfaced with host computer, APPLE- ll . This enables the processor to develop and simulate various digital signal processing algorithms. The performance of the processor was evaluated by the Fast Fourier Transform (FFT) program. The execution time to perform 16 bit 1024 points complex FF7, radix-2 DIT algorithm, was about 175 msec with IMHz master Clock. We can use this processor to Bevelop more efficient signal processing algorithms on the biological signal processing.

• 산업경영시스템학회지
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• 제23권57호
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• pp.1-10
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• 2000

The purpose of this paper is to propose a method of rest to reduce work load of night shift workers for night shift work. The experiment was carried out 10minutes preparing time, 45minutes first work, 10minutes first rest, 45minutes second work, 10minutes second rest between 2 and 4 o'clock that the lowest physiological function of workers. The methods of rest set up as four patterns (1) non-action rest (2) non-action rest + listening music (3) action rest + non-action rest, (4) action rest + non-action rest + listening music. For the measurements of experiment, heart rates(R-R interval), critical flicker fusion frequency(CFF), blood pressure, oral temperature, reaction time and error rates were considered as criteria for work performance. As a result, action rest + non-action rest and action rest + non-action rest + listening music were more effective to reduce work load additional work than non-action rest and non-action rest + listening music.