• Physical Therapy Rehabilitation Science
• /
• v.6 no.3
• /
• pp.134-139
• /
• 2017

Objective: Dual-task interference is defined as decrements in performance observed when people attempt to perform two tasks concurrently, such as a verbal task and walking. The purpose of this study was to investigate the changes of gait ability according to the dual task interference in chronic stroke survivors. Design: Cross-sectional study. Methods: Ten chronic stroke survivors (9 male, 1 female; mean age, 55.30 years; mini mental state examination, 19.60; onset duration, 56.90 months) recruited from the local community participated in this study. Gait ability (velocity, paretic side step, and stride time and length) under the single- and dual-task conditions at a self-selected comfortable walking speed was measured using the motion analysis system. In the dual task conditions, subjects performed three types of cognitive tasks (controlled oral word association test, auditory clock test, and counting backwards) while walking on the track. Results: For velocity, step and stride length, there was a significant decrease in the dual-task walking condition compared to the single walking condition (p<0.05). In particular, higher reduction of walking ability was observed when applying the counting backward task. Conclusions: Our results revealed that the addition of cognitive tasks while walking may lead to decrements of gait ability in stroke survivors. In particular, the difficulty level was the highest for the calculating task. We believe that these results provide basic information for improvements in gait ability and may be useful in gait training to prevent falls after a stroke incident.

• Journal of Engineering Education Research
• /
• v.2 no.1
• /
• pp.10-16
• /
• 1999

In this paper, we developed the internet-based educational software package (DVLab) for design and virtual experiment of the digital logic circuits. The DVLab consists of the LogicSim module for design and simulation of digital combinational/sequantial logic circuits, micro-controller application circuits and the BreadBoard module for virtual experiment and the Theory module for lecture and the Report/ReportChecker module and some other utility modules. All developed modules can be run as application programs as well as applets in the Internet. The LogicSim and the BreadBoard support real time clock function, output verification function on the designed circuits, trace function of logic values, copy-protection function of designed circuits and provide various devices including logic gates, TTLs, LED, buzzer, and micro-controller. The educational model of digital logic circuit design and experiment using the DVLab is also presented in this paper.

• Journal of the Korean Home Economics Association
• /
• v.33 no.6
• /
• pp.245-253
• /
• 1995

The purpose of this study was to investigate the fatty acid composition and the rancidity of commercial deep-fat fried foods in Kangreung. the 7 kinds of samples were purchased form snack corners in 3 markets at AM 10 and PM 6 o'clock. The acid value, peroxide value and TBA value of the deep-fat fried foods were determined and the fatty acid composition were analyzed. The range of acid value was 0.45∼1.79, that of peroxide value was 1.24∼8.64meq/㎏,and that of TBA value was 12∼140 in all samples. There was significant difference in most of all samples by purchasing time and kinds of samples. But there was not specific tendency by purchasing times in each sample. Most of the acid value, peroxide value and TBA value of the samples fried with meats or sea foods showed higher value than the that of samples fried with vegetables or seaweeds. The fatty acid composition of the total lipids in the deep-fat fried foods were similar to one another. The major fatty acids were linoleic acid(C18 : 2) , oleic acid(C18 : 1) in order of content. Minor fatty acids were palmitic acid(C16 :0), linolenic acid(C18 : 3), stearic acid (C18 : 0) in order of content. the P/S ratio was the range of 2.12/1∼4.71/1 and the that of the samples fried with meats was the highest among samples. so there was the same tendency in this result between the chemical properties(acid value, peroxide value, TBA Value) and fatty acid composition. As a result of acid value and peroxide value in this study, the commercial deep-fat fried foods in Kangreung was safety.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.14 no.1
• /
• pp.8-13
• /
• 2003

In this paper, suitablility of 1 GHz CISPR limits establishment fur broadcast communication quality protection is examined and the optimum turn step resolution of EUT for spurious measurement of frequency above 1 GHz to increase the accuracy of maximum values extraction is examined. As a result of 500 MHz and 1.7 GHz clock speed personal computer of micro-processor measurement, optimum turn step resolution extracted by National Institution of National Instrument of Standard & Technology(NIST) Koepke method is estimated 40 table positions per polarization in 500 MHz. And in case of 1.7 GHz, step size is 36 table positions. Prediction of turn step size required for fully scan method in gjgahertz measurement will increase measurement accuracy and reduce considerable measurement time as well.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.26 no.3
• /
• pp.333-341
• /
• 2015

In this paper, a 0.5~4 GHz frequency synthesizer having good phase noise performance is proposed. Wideband output frequencies of the synthesizer were synthesized using DDS(Direct Digital Synthesizer) and analog direct frequency synthesis technology in order to obtain fast settling time. Also in order to get good phase noise performance, 2.4 GHz DDS clock was generated by VCO(Voltage Controlled Oscillator) which was locked by the 100 MHz reference oscillator using SPD(Sample Phase Detector). The phase noise performance of wideband frequency synthesizer was estimated and the results were compared with the measured ones. The measured phase noise of the frequency synthesizer was less then -121 dBc @ 100 kHz at 4 GHz.

• Proceedings of the Korean Society of Computational and Applied Mathematics Conference
• /
• 2003.09a
• /
• pp.11-11
• /
• 2003

오늘날 단일 슈퍼컴퓨터로는 처리가 불가능한 거대한 문제들의 해법이 시도되고 있는데, 이들은 지리적으로 분산된 슈퍼컴퓨터, 데이터베이스, 과학장비 및 디스플레이 장치 등을 초고속 통신망으로 연결한 GRID 환경에서 효과적으로 실행시킬 수 있다. GRID는 1990년대 중반 과학 및 공학용 분산 컴퓨팅의 연구 과정에서 등장한 것으로, 점차 응용분야가 넓어지고 있다. 그러나 GRID 같은 분산 환경은 기존의 단일 병렬 시스템과는 많은 점에서 다르며 이전의 기술들을 그대로 적용하기에는 무리가 있다. 기존 병렬 시스템에서는 주로 동기 알고리즘(synchronous algorithm)이 사용되는데, 직렬 연산과 같은 결과를 얻기 위해 동기화(synchronization)가 필요하며, 부하 균형이 필수적이다. 그러나 부하 균형은 이질 클러스터(heterogeneous cluster)처럼 프로세서들의 성능이 서로 다르거나, 지리적으로 분산된 계산자원을 사용하는 GRID 환경에서는 이기종의 문제뿐 아니라 네트워크를 통한 메시지의 전송 지연 등으로 유휴시간이 길어질 수밖에 없다. 이처럼 동기화의 필요성에 의한 연산의 지연을 해결하는 하나의 방안으로 비동기 반복법(asynchronous iteration)이 나왔으며, 지금도 활발히 연구되고 있다. 이는 알고리즘의 동기점을 가능한 한 제거함으로써 빠른 프로세서의 유휴 시간을 줄이는 것이 목적이다. 즉 비동기 알고리즘에서는, 각 프로세서는 다른 프로세서로부터 갱신된 데이터가 올 때까지 기다리지 않고 계속 다음 작업을 수행해 나간다. 따라서 동시에 갱신된 데이터를 교환한 후 다음 단계로 진행하는 동기 알고리즘에 비해, 미처 갱신되지 않은 데이터를 사용하는 경우가 많으므로 전체적으로는 연산량 대비의 수렴 속도는 느릴 수 있다 그러나 각 프로세서는 거의 유휴 시간이 없이 연산을 수행하므로 wall clock time은 동기 알고리즘보다 적게 걸리며, 때로는 50%까지 빠른 결과도 보고되고 있다 그러나 현재까지의 연구는 모두 어떤 수렴조건을 만족하는 선형 시스템의 해법에 국한되어 있으며 비교적 구현하기 쉬운 공유 메모리 시스템에서의 연구만 보고되어 있다. 본 연구에서는 행렬의 주요 고유쌍을 구하는 데 있어 비동기 반복법의 적용 가능성을 타진하기 위해 우선 이론적으로 단순한 멱승법을 사용하여 실험하였고 그 결과 순수한 비동기 반복법은 수렴하기 어렵다는 결론을 얻었다 그리하여 동기 알고리즘에 비동기적 요소를 추가한 혼합 병렬 알고리즘을 제안하고, MPI(Message Passing Interface)를 사용하여 수원대학교의 Hydra cluster에서 구현하였다. 그 결과 특정 노드의 성능이 다른 것에 비해 현저하게 떨어질 때 전체적인 알고리즘의 수렴 속도가 떨어지는 것을 상당히 완화할 수 있음이 밝혀졌다.

• KSCE Journal of Civil and Environmental Engineering Research
• /
• v.37 no.2
• /
• pp.459-466
• /
• 2017

Several reservoirs that were managed by local governments and the Korea Rural Community Corporation have recently collapsed. One of them is the Goeyeon reservoir in Yeongcheon-si, Gyeongsangbuk-do that collapsed mainly around the spillway due to heavy rain at 9 O'clock, on 21 August 2014. The Goeyeon reservoir was an aging agricultural reservoir over 70 years since it was built. In this study, the collapse situation of the reservoir was reproduced through the DAMBRK model. Flood inundation maps were reconstructed for the breach outflow of the dam analyzed by the DAMBRK model. We estimated the breach duration and outflow of the reservoir as compared with the inundation image taken by the Unmanned Aerial Vehicle (UAV) at the time when the Goeyeon reservoir collapsed. The results of this study are expected to be useful for predicting damage in the downstream inundation area when a reservoir collapses.

• Journal of Environmental Science International
• /
• v.27 no.8
• /
• pp.723-735
• /
• 2018

In this study, to investigate an optimal configuration method for the modeling system, we performed an optimization experiment by controlling the types of compilers and libraries, and the number of CPU cores because it was important to provide reliable model data very quickly for the national air quality forecast. We were made up the optimization experiment of twelve according to compilers (PGI and Intel), MPIs (mvapich-2.0, mvapich-2.2, and mpich-3.2) and NetCDF (NetCDF-3.6.3 and NetCDF-4.1.3) and performed wall clock time measurement for the WRF and CMAQ models based on the built computing resources. In the result of the experiment according to the compiler and library type, the performance of the WRF (30 min 30 s) and CMAQ (47 min 22 s) was best when the combination of Intel complier, mavapich-2.0, and NetCDF-3.6.3 was applied. Additionally, in a result of optimization by the number of CPU cores, the WRF model was best performed with 140 cores (five calculation servers), and the CMAQ model with 120 cores (five calculation servers). While the WRF model demonstrated obvious differences depending on the number of CPU cores rather than the types of compilers and libraries, CMAQ model demonstrated the biggest differences on the combination of compilers and libraries.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
• /
• v.10 no.4
• /
• pp.304-310
• /
• 2017

In this paper, we propose the architecture of an IPM based lane detector for autonomous vehicles to detect and control the driving route along the curved lane. In the IPM image, we divide the area into two fields, Far/Near Field, and the lane candidate region is detected using the Hough transform to perform the matching for the curved lane. In autonomous vehicles, various algorithms must be embedded in the system. To reduce the system resources, we proposed a method to minimize the number of memory accesses to the image and various parameters on the external memory. The proposed circuit has 96% lane recognition rate and occupies 16% LUT, 5.9% FF and 29% BRAM in Xilinx XC7Z020. It processes Full-HD image at a rate of 42 fps at a 100 MHz operating clock.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.20 no.1
• /
• pp.110-116
• /
• 2016

This paper describes 1.2-V 5-Gb/s scalable low voltage signaling(SLVS) differential transmitter(TX) with a digital impedance calibration and equalizer. The proposed transmitter consists of a phase-locked loop(PLL) with 4-phase output clock, a 4-to-1 serializer, a regulator, an output driver, and an equalizer driver for improvement of the signal integrity. A pseudo random bit sequence generator is implemented for a built-in self-test. The proposed SLVS transmitter provides the output differential swing level from 80mV to 500mV. The proposed SLVS transmitter is implemented by using a 65-nm CMOS with a 1.2-V supply. The measured peak-to-peak time jitter of the implemented SLVS TX is about 46.67 ps at the data rate of 5Gb/s. Its power consumption is 1.88 mW/Gb/s.