• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.1
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• pp.20-27
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• 2010

This paper describes a design of 5-stage pipelined de-blocking filter with power reduction scheme and proposes a efficient memory architecture and filter order for high performance H.264/AVC Decoder. Generally the de-blocking filter removes block boundary artifacts and enhances image quality. Nevertheless filter has a few disadvantage that it requires a number of memory access and iterated operations because of filter operation for 4 time to one edge. So this paper proposes a optimized filter ordering and efficient hardware architecture for the reduction of memory access and total filter cycles. In proposed filter parallel processing is available because of structured 5-stage pipeline consisted of memory read, threshold decider, pre-calculation, filter operation and write back. Also it can reduce power consumption because it uses a clock gating scheme which disable unnecessary clock switching. Besides total number of filtering cycle is decreased by new filter order. The proposed filter is designed with Verilog-HDL and functionally verified with the whole H.264/AVC decoder using the Modelsim 6.2g simulator. Input vectors are QCIF images generated by JM9.4 standard encoder software. As a result of experiment, it shows that the filter can make about 20% total filter cycles reduction and it requires small transposition buffer size.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.10
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• pp.2307-2314
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• 2015

This paper focuses on the generation algorithm of BeiDou pseudorange correction (PRC) and simulation based performance verification for design of Differential Global Navigation Satellite System (DGNSS) reference station and integrity monitor (RSIM) in order to prepare for recapitalization of DGNSS. First of all, it discusses the International standard on DGNSS RSIM, based on the interface control document (ICD) for BeiDou, estimates the satellite position using satellite clock offset and user receiver clock offset, and the system time offset between Global Positioning System (GPS) and BeiDou. Using the performance verification platform interfaced with GNSS (GPS/BeiDou) simulator, it calculates the BeiDou pseudorange corrections , compares the results of position accuracy with GPS/DGPS. As the test results, this paper verified to meet the performance of position accuracy for DGNSS RSIM operation required on Radio Technical Commission for Maritime Services (RTCM) standard.

• Molecules and Cells
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• v.41 no.8
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• pp.742-752
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• 2018

Parkinson's disease (PD) is a neurodegenerative disease characterized by progressive degeneration of dopaminergic (DAergic) neurons, particularly in the substantia nigra (SN). Although circadian dysfunction has been suggested as one of the pathophysiological risk factors for PD, the exact molecular link between the circadian clock and PD remains largely unclear. We have recently demonstrated that $REV-ERB{\alpha}$, a circadian nuclear receptor, serves as a key molecular link between the circadian and DAergic systems. It competitively cooperates with NURR1, another nuclear receptor required for the optimal development and function of DA neurons, to control DAergic gene transcription. Considering our previous findings, we hypothesize that $REV-ERB{\alpha}$ may have a role in the onset and/or progression of PD. In the present study, we therefore aimed to elucidate whether genetic abrogation of $REV-ERB{\alpha}$ affects PD-related phenotypes in a mouse model of PD produced by a unilateral injection of 6-hydroxydopamine (6-OHDA) into the dorsal striatum. $REV-ERB{\alpha}$ deficiency significantly exacerbated 6-OHDA-induced motor deficits as well as DAergic neuronal loss in the vertebral midbrain including the SN and the ventral tegmental area. The exacerbated DAergic degeneration likely involves neuroinflammation-mediated neurotoxicity. The $REV-erb{\alpha}$ knockout mice showed prolonged microglial activation in the SN along with the over-production of interleukin $1{\beta}$, a pro-inflammatory cytokine, in response to 6-OHDA. In conclusion, the present study demonstrates for the first time that genetic abrogation of $REV-ERB{\alpha}$ can increase vulnerability of DAergic neurons to neurotoxic insults, such as 6-OHDA, thereby implying that its normal function may be beneficial for maintaining DAergic neuron populations during PD progression.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.13 no.5
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• pp.359-369
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• 2020

In this paper, we proposed a charge pump (CP) circuit that has a wide operating range while reducing the current mismatch for the PLL that generates the main clock of the CMOS X-Ray detector. The operating range and current mismatch of the CP circuit are determined by the characteristics of the current source circuit for the CP circuit. The proposed CP circuit is implemented with a wide operating current mirror bias circuit to secure a wide operating range and a cascode structure with a large output resistance to reduce current mismatch. The proposed wide operating range cascode CP circuit was fabricated as a chip using a 350nm CMOS process, and current matching characteristics were measured using a source measurement unit. At this time, the power supply voltage was 3.3 V and the CP circuit current ICP = 100 ㎂. The operating range of the proposed CP circuit is △VO_Swing=2.7V, and the maximum current mismatch is 5.15 % and the maximum current deviation is 2.64 %. The proposed CP circuit has low current mismatch characteristics and can cope with a wide frequency range, so it can be applied to systems requiring various clock speed.

• The KIPS Transactions:PartA
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• v.8A no.4
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• pp.479-488
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• 2001

As the SoC designs complexity constantly increases, the simulation that uses their software models simply takes too much time. To solve this problem, FPGA-based logic emulators have been developed and commonly used in the industry. However, FPGA-based logic emulators are facing with the problems of which not only very low FPGA resource usage rate due to the very limited number of pins in FPGAs, but also the emulation speed getting slow drastically as the complexity of designs increases. In this paper, we proposed a new innovative emulation architecture and its software that has high FPGA resource usage rate and makes the emulation extremely fast. The proposed emulation system has merits to overcome the FPGA pin limitation by pipelined ring which transfers multiple logic signal through a single physical pin, and it also makes possible to use a high speed system clock through the intelligent ring topology. In this topology, not only all signal transfer channels among EPGAs are totally separated from user logic so that a high speed system clock can be used, but also the depth of combinational paths is kept swallow as much as possible. Both of these are contributed to achieve high speed emulation. For pipelined singnals transfer among FPGAs we adopt a few heuristic scheduling having low computation complexity. Experimental result with a 12 bit microcontroller has shown that high speed emulation possible even with these simple heuristic scheduling algorithms.

• Publications of The Korean Astronomical Society
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• v.36 no.3
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• pp.79-95
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• 2021

This study aims to develop a restoration model of an armillary sphere of Tongcheon-ui (Pan-celestial Armillary Sphere) by referring to the records of Damheonseo (Hong Dae-Yong Anthology) and the artifact of an armillary sphere in the Korean Christian Museum of Soongsil University. Between 1760 and 1762, Hong, Dae-Yong (1731-1783) built Tongcheon-ui, with Na, Kyung-Jeok (1690-1762) designing the basic structure and Ann, Cheo-In (1710-1787) completing the assembly. The model in this study is a spherical body with a diameter of 510 mm. Tongcheon-ui operates the armillary sphere by transmitting the rotational power from the lantern clock. The armillary sphere is constructed in the fashion of a two-layer sphere: the outer one is Yukhab-ui that is fixed; and the inner one, Samsin-ui, is rotated around the polar axis. In the equatorial ring possessed by Samsin-ui, an ecliptic ring and a lunar-path ring are successively fixed and are tilted by 23.5° and 28.5° over the equatorial ring, respectively. A solar miniature attached to a 365-toothed inner gear on the ecliptic ring reproduces the annual motion of the Sun. A lunar miniature installed on a 114-toothed inner gear of the lunar-path ring can also replay the moon's orbital motion and phase change. By the set of 'a ratchet gear, a shaft and a spur gear' installed in the solstice-colure double-ring, the inner gears in the ecliptic ring and lunar-path ring can be rotated in the opposite direction to the rotation of Samsin-ui and then the solar and lunar miniatures can simulate their revolution over the period of a year and a month, respectively. In order to indicate the change of the moon phases, 27 pins were arranged in a uniform circle around the lunar-path ring, and the 29-toothed wheel is fixed under the solar miniature. At the center of the armillary sphere, an earth plate representing a world map is fixed horizontally. Tongcheon-ui is the armillary sphere clock developed by Confucian scholars in the late Joseon Dynasty, and the technical level at which astronomical clocks could be produced at the time is of a high standard.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.45 no.9
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• pp.13-19
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• 2008

Time synchronization of nodes in sensor network synchronizes sensor nodes to one time clock. This is very essential in sensor networks so that the information collected and reported from the sensor nodes becomes meaningful. If sensor nodes are not synchronized, disaster report with time information can be wrong analyzed and this may lead to big calamity. With the limitation of battery and computing power, time synchronization algorithm imported in sensor nodes has to be as simple as it doesn't need big complexity, nor generates many synchronization messages. To reduce the synchronization error, hop count should be kept small between reference node to initiate synchronization and sensor nodes to be synchronized. Therefore, multiple reference nodes are used instead of single reference node. The use of multiple reference nodes introduce the requirement of synchronization among reference nodes in the network. Several algorithms have been proposed till now, but the synchronization among reference nodes are not well considered. This paper proposes improved time synchronization for sensor networks by synchronizing multiple reference nodes inside the network. Through simulation, we validated the effects of new algorithm.

• Horticultural Science & Technology
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• v.28 no.3
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• pp.409-414
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• 2010

The first drainage time in a day was controlled for precise irrigation management with low consumption of nutrient solution in tomato perlite bag culture system by measuring water level of drained water in drainage catchment part. This method automatically adjusted the irrigation time under any condition of light, temperature and humidity, resulting in stable water content in substrates. However, it was difficult to keep the time consistent as they were set. It drained with the deviation of 20 min in the treatment in which the first drainage time was set at 10:00 and 50 min in the treatment set at 10:30. The first drainage time was not constant, but the drain occurred stably before noon in the treatment of which irrigation frequency was longer than 30 min. The drainage ratio was better balanced in all the treatments using drainage level sensors than the treatment using time clock for irrigation control. High water and fertilizer efficiencies were obtained. Although the growth, total yield and sugar content were not significantly different between the treatments, fruit weight was higher in the treatments using drainage level sensors than that using timer.

• Cross-Cultural Studies
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• v.50
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• pp.225-259
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• 2018

In this study, according to the Institut d'Estudis Catalan, it is noted that the traditional Catalan time telling system is essentially based on delineating time by the use of the 'quarts (=quarters)' of an hour. In this fasion, to tell the time 8:15, 8:30 and 8:45 they use '${\acute{E}}s$ un quart de nou.,' '$S{\acute{o}}n$ dos quarts de nou.,' and '$S{\acute{o}}n$ tres quarts de nou.,' but do not use constructions such as '$S{\acute{o}}n$ les vuit i quinze.,' '$S{\acute{o}}n$ les vuit i trenta/mitja.,' '$S{\acute{o}}n$ les vuit i quaranta-cinc.,' because these expressions are considered to be as dialectal variants or international notation-based variants. Moreover, the traditional Catalan time telling system does not use cardinal numbers, except in the case of 'cinc (five)' and 'deu (ten).' These linguistic phenomenon cause the invention of a unique Catalan digital watch, and has noted special designs for the creation of a Catalan analogue watch. For this reason, the quarter system in colloquial Catalan provokes an enormous interpretative ambiguity in daily routine expressions with 'quarts' like '$S{\acute{o}}n$ quarts of nou.' or 'entre dos i tres quarts' whose meaning is not delineated between sixteen and forty-four minutes. We will argue that the traditional Catalan time telling expressions do not have the use of the subtractive system, and the fraction word 'quart' lacks a specific meaning of fifteen minutes because the Catalan word 'quart' is etymologically related to the classical public bell system, not definitively to the traditional clock system.

• KIPS Transactions on Computer and Communication Systems
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• v.11 no.10
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• pp.373-380
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• 2022

This paper presents a deep learning based group synchronization that supports networked immersive interactions between remote users. The goal of group synchronization is to enable all participants to synchronously interact with others for increasing user presence Most previous methods focus on NTP-based clock synchronization to enhance time accuracy. Moving average filters are used to control media playout time on the synchronization server. As an example, the exponentially weighted moving average(EWMA) would be able to track and estimate accurate playout time if the changes in input data are not significant. However it needs more time to be stable for any given change over time due to codec and system loads or fluctuations in network status. To tackle this problem, this work proposes the Deep Group Synchronization(DeepGroupSync), a group synchronization based on deep learning that models important features from the data. This model consists of two Gated Recurrent Unit(GRU) layers and one fully-connected layer, which predicts an optimal playout time by utilizing the sequential playout delays. The experiments are conducted with an existing method that uses the EWMA and the proposed method that uses the DeepGroupSync. The results show that the proposed method are more robust against unpredictable or rapid network condition changes than the existing method.