• Journal of Astronomy and Space Sciences
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• v.28 no.1
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• pp.55-62
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• 2011

The precise orbit determination (POD) of low earth orbiter (LEO) has complied with its required positioning accuracy by the double-differencing of observations between International GNSS Service (IGS) and LEO to eliminate the common clock error of the global positioning system (GPS) satellites and receiver. Using this method, we also have achieved the 1 m positioning accuracy of Korea Multi-Purpose Satellite (KOMPSAT)-2. However double-differencing POD has huge load of processing the global network of lots of ground stations because LEO turns around the Earth with rapid velocity. And both the centimeter accuracy and the near real time (NRT) processing have been needed in the LEO POD applications--atmospheric sounding or urgent image processing--as well as the surveying. An alternative to differential GPS for high accuracy NRT POD is precise point positioning (PPP) to use measurements from one satellite receiver only, to replace the broadcast navigation message with precise post processed values from IGS, and to have phase measurements of dual frequency GPS receiver. PPP can obtain positioning accuracy comparable to that of differential positioning. KOMPSAT-5 has a precise dual frequency GPS flight receiver (integrated GPS and occultation receiver, IGOR) to satisfy the accuracy requirements of 20 cm positioning accuracy for highly precise synthetic aperture radar image processing and to collect GPS radio occultation measurements for atmospheric sounding. In this paper we obtained about 3-5 cm positioning accuracies using the real GPS data of the Gravity Recover and Climate Experiment (GRACE) satellites loaded the Blackjack receiver, a predecessor of IGOR. And it is important to reduce the latency of orbit determination processing in the NRT POD. This latency is determined as the volume of GPS measurements. Thus changing the sampling intervals, we show their latency to able to reduce without the precision degradation as the assessment of their precision.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.46 no.1
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• pp.76-81
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• 2009

A novel design method of time-interleaved subranging ADC is presented. We use the bisection method to let only half of comparators in typical subranging ADC working in every clock cycle. Thus, we are able to reduce the number of comparators by half. It is possible to reduce the die size. An example of 8-bit time-interleaved subranging ADC operates at 40MHz sampling rate and 1.8V supply voltage is demonstrated. The power consumption of the proposed circuit is only 10mV with SPECTRE simulation. Compared with the typical subranging ADC, our bisection method is able to reduce up to 40% in die size.

• The Journal of the Acoustical Society of Korea
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• v.13 no.2E
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• pp.58-67
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• 1994

Hidden Markov Model (HMM)-based algorithms have been used successfully in many speech recognition systems, especially large vocabulary systems. Although general purpose processors can be employed for the system, they inevitably suffer from the computational complexity and enormous data. Therefore, it is essential for real-time speech recognition to develop specialized hardware to accelerate the recognition steps. This paper concerns with a real-time implementation of an isolated word recognition system based on HMM. The speech recognition system consists of a host computer (PC), a DSP board, and a prototype Viterbi scoring board. The DSP board extracts feature vectors of speech signal. The Viterbi scoring board has been implemented using three field-programmable gate array chips. It employs a hardware-efficient Viterbi scoring architecture and performs the Viterbi algorithm for HMM-based speech recognition. At the clock rate of 10 MHz, the system can update about 100,000 states within a single frame of 10ms.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.49 no.1
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• pp.85-91
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• 2012

In this paper, we implemented a Ka-band frequency synthesizer for millimeter wave seeker. we designed for high frequency resolution and frequency hopping response time in the digital synthesis method which uses DDS(Direct Digital Synthesizer). but frequency bandwidth was limited low frequency because DDS output frequency was limited 1/2 by system clock. thus, frequency synthesizer was converted to Ka-band using the frequency multiplier ${\times}4$ and local oscillator. proposed frequency synthesizer was bandwidth 500MHz, frequency switching time was $0.7{\mu}s$, spurious level was suppressed below -52dBc. phase noise was -99dBc/Hz at offset 100kHz and flatness was ${\pm}1dB$.

• The Journal of the Korea institute of electronic communication sciences
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• v.11 no.11
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• pp.1061-1068
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• 2016

A theme park runs various programs to provide users entertainments. Among the programs of the theme park, amusement facilities are the most favorite ones used by the users. However, Since the waiting time of the amusement facilities becomes increasing due to the large number of the users, the satisfaction of the users is diminished heavily, To solve this problem, we propose a reservation system for amusement facility using near field communication. In the proposed system, a server appends the user to the waiting queue of the amusement facility when an user contacts the reader of an amusement facility using NFC, If an clock approaches to the time that the user will exploit the amusement facility, the server notifies to the user. The implemented reservation system has the benefit to provide the user chances to exploit other programs during the waiting time.

• Journal of Navigation and Port Research
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• v.35 no.8
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• pp.619-624
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• 2011

A significant factor limiting the ranging accuracy of Loran (Long Range Navigation) signal is the additional secondary factor (ASF) in the time of arrival (TOA) measurements. Precise ASF values are essential if Loran deliver the high absolute accuracies demanded for aircraft approach, maritime harbour entrance. We measured the absolute propagation delay between Pohang Loran signal and Loran receiver output signal by comparing with Cesium atomic clock. In this study we measured ASFs between Pohang 9930M station and the 12 measurement points in the Yeongil Bay by using the measurement technique of absolute time delay. The measurement points were spaced at interval of 3 km by 3 km. An E-field antenna and an H-field antenna were used to improve the accuracy of ASF measurements and a DGPS (Differential GPS) receiver was used for accurate positions. We have gotten the result that the measured ASFs were compared with the predicted ASFs through this measurement technique.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.5A
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• pp.554-565
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• 2004

In this paper, we implement single cycle and multi cycle adders. We can compare area and time by using the implemented adders. The size of adders is 64, 128, 256-bits. The architecture of hybrid adders is that the carry-out of small adder groups can be interconnected by utilizing n carry propagate unit. The size of small adder groups is selected in three formats - 4, 8, 16-bits. These adders were implemented with Verilog HDL with top-down methodology, and they were verified by behavioral model. The verified models were synthesized with a Samsung 0,35(um), 3.3(V) CMOS standard cell library while a using Synopsys Design Compiler. All adders were synthesized with group or ungroup. The optimized adder for a Crypto-processor included Smart Card IC is that a 64-bit RCA based on 16-bit CLA. All small adder groups in this optimized adder were synthesized with group. This adder can operate at a clock speed of 198 MHz and has about 961 gates. All adders can execute operations in this won case conditions of 2.7 V, 85 $^{\circ}C$.

• Journal of the Korean Institute of Telematics and Electronics
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• v.25 no.9
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• pp.1115-1124
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• 1988

A two-dimensional systolic array for fast Fourier transform, which has a regular and recursive VLSI architecture is presented. The array is constructed with identical processing elements (PE) in mesh type, and due to its modularity, it can be expanded to an arbitrary size. A processing element consists of two data routing units, a butterfly arithmetic unit and a simple control unit. The array computes FFT through three procedures` I/O pipelining, data shuffling and butterfly arithmetic. By utilizing parallelism, pipelining and local communication geometry during data movement, the two-dimensional systolic array eliminates global and irregular commutation problems, which have been a limiting factor in VLSI implementation of FFT processor. The systolic array executes a half butterfly arithmetic based on a distributed arithmetic that can carry out multiplication with only adders. Also, the systolic array provides 100% PE activity, i.e., none of the PEs are idle at any time. A chip for half butterfly arithmetic, which consists of two BLC adders and registers, has been fabricated using a 3-um single metal P-well CMOS technology. With the half butterfly arithmetic execution time of about 500 ns which has been obtained b critical path delay simulation, totla FFT execution time for 1024 points is estimated about 16.6 us at clock frequency of 20MHz. A one-PE chip expnsible to anly size of array is being fabricated using a 2-um, double metal, P-well CMOS process. The chip was layouted using standard cell library and macrocell of BLC adder with the aid of auto-routing software. It consists of around 6000 transistors and 68 I/O pads on 3.4x2.8mm\ulcornerarea. A built-i self-testing circuit, BILBO (Built-In Logic Block Observation), was employed at the expense of 3% hardware overhead.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.37 no.3
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• pp.55-62
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• 2000

This paper presents an analysis of the chaotic behavior in the discrete-time voltage mode chaotic generator fabricated using 0.8${\mu}{\textrm}{m}$ single poly CMOS technology. An approximated empirical equation is extracted from the measurement data of a nonlinear function block. Then the bifurcation diagram is simulated according to input variables and Lyapunov exponent λ which represent a dependence on an initial value is calculated. We show the interrelations among time waveforms, state transition, and power spectra for the state condition of chaotic circuit, such as equilibrium, periodic, and chaotic state. And results of experiments in the chaotic circuit with the $\pm$2.5V power supply and sampling clock frequency of 10KHz are shown and compared with the simulated results.

• Journal of Radiation Protection and Research
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• v.2 no.1
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• pp.9-16
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• 1977

A simple method has been established for determining RaA, RaB and RaC concentrations in airborne dust. This is to evaluate the concentration from measurement of total alpha activities in three selected-time intervals after an air sample is taken from the membrane filter paper (mean pore size: $0.8{\mu}m$). As a preliminary trial, a time-variation of the concentrations has been determined using the single-filter method at the KAERI site (N. Lat. $37^{\circ}38'$ and E. Long $127^{\circ}15'$), Seoul, Korea. It appears that there is a large variation of the concentrations depending on the sampling time. Generally the highest value was observed in the morning that may coincide with the highest density of atmosphere in a day while the lowest value was obtained around fourteen o'clock.