• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2007.11a
• /
• pp.117-117
• /
• 2007

The physical and electrical properties of nitrided Hf-silicate films, incorporated by NO gas annealing, were investigated by XPS, NEXAFS, TEM and C-V measurement. We confirmed the nitrogen incorporation during NO gas annealing treatment effectively enhances the thermal stability of Hf-silicate. The suppression of phase separation was observed in Hf-silicate films with high nitrogen contents. The negative shift of threshold voltage is caused by the incorporation of nitrogen in the hafnium silicate films.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2010.06a
• /
• pp.11-11
• /
• 2010

Thin-film-transistors (TFTs) that can be deposited at low temperature have recently attracted lots of applications such as sensors, solar cell and displays, because of the great flexible electronics and transparent. Transparent and flexible transistors are being required that high mobility and large-area uniformity at low temperature [1]. But, unfortunately most of TFT structures are used to be $SiO_2$ as gate dielectric layer. The $SiO_2$ has disadvantaged that it is required to high driving voltage to achieve the same operating efficiency compared with other high-k materials and its thickness is thicker than high-k materials [2]. To solve this problem, we find lots of high-k materials as $HfO_2$, $ZrO_2$, $SiN_x$, $TiO_2$, $Al_2O_3$. Among the High-k materials, $Al_2O_3$ is one of the outstanding materials due to its properties are high dielectric constant ( ~9 ), relatively low leakage current, wide bandgap ( 8.7 eV ) and good device stability. For the realization of flexible displays, all processes should be performed at very low temperatures, but low temperature $Al_2O_3$ grown by sputtering showed deteriorated electrical performance. Further decrease in growth temperature induces a high density of charge traps in the gate oxide/channel. This study investigated the effect of growth temperatures of ALD grown $Al_2O_3$ layers on the TFT device performance. The ALD deposition showed high conformal and defect-free dielectric layers at low temperature compared with other deposition equipments [2]. After ITO was wet-chemically etched with HCl : $HNO_3$ = 3:1, $Al_2O_3$ layer was deposited by ALD at various growth temperatures or lift-off process. Amorphous InGaZnO channel layers were deposited by rf magnetron sputtering at a working pressure of 3 mTorr and $O_2$/Ar (1/29 sccm). The electrodes were formed with electron-beam evaporated Ti (30 nm) and Au (70 nm) bilayer. The TFT devices were heat-treated in a furnace at $300^{\circ}C$ and nitrogen atmosphere for 1 hour by rapid thermal treatment. The electrical properties of the oxide TFTs were measured using semiconductor parameter analyzer (4145B), and LCR meter.

• Proceedings of the Korean Society Of Semiconductor Equipment Technology
• /
• 2007.06a
• /
• pp.193-198
• /
• 2007

The NiSi is very promising candidate for the metallization in 60nm CMOS process such as FUSI(fully silicided) gate and source/drain contact because it exhibits non-size dependent resistance, low silicon consumption and mid-gap workfunction. Ni film was first deposited by using ALD (atomic layer deposition) technique with Bis-Ni precursor and $H_2$ reactant gas at $220^{\circ}C$ with deposition rate of $1.25{\AA}/cycle$. The as-deposited Ni film exhibited a sheet resistance of $5{\Omega}/{\square}$. RTP (repaid thermal process) was then performed by varying temperature from $400^{\circ}C$ to $900^{\circ}C$ in $N_2$ ambient for the formation of NiSi. The process window temperature for the formation of low-resistance NiSi was estimated from $600^{\circ}C$ to $800^{\circ}C$ and from $700^{\circ}C$ to $800^{\circ}C$ with and without Ti capping layer. The respective sheet resistance of the films was changed to $2.5{\Omega}/{\square}$ and $3{\Omega}/{\square}$ after silicidation. This is because Ti capping layer increases reaction between Ni and Si and suppresses the oxidation and impurity incorporation into Ni film during silicidation process. The NiSi films were treated by additional thermal stress in a resistively heated furnace for test of thermal stability, showing that the film heat-treated at $800^{\circ}C$ was more stable than that at $700^{\circ}C$ due to better crystallinity.

• Proceedings of the Korean Institute of Surface Engineering Conference
• /
• 2012.05a
• /
• pp.150-150
• /
• 2012

본 연구는 1차원 나노 구조의 합성과 기초적 분석에 관한 연구로써 특히 무기 산화물 나노재료를 그 대상으로 하였다. 내용으로는 첫째, 1차원 코어 나노와이어의 합성을 하였고 Thermal evaporation, substrate의 가열, 그리고 MOCVD 를 사용한 결과들을 나열한다. 둘째, 코어-쉘 나노와이어를 제작하기 위하여 특히 쉘층의 제작방법을 연구하였는데 PECVD, ALD, 그리고 sputtering에 의한 결과들을 나열하고 간단히 설명한다. Thermal evaporation에 의한 1차원 나노와이어 합성의 경우는 MgO의 예를 들었는데 MgO 나노와이어는 Au가 증착된 기판을 열처리하여 Au dot를 형성하고 이의 morphology를 조절하여 최적의 나노와이어 합성조건을 선정하였다. 이로써 기판 morphology가 나노선의 성장및 형상에 영향을 준다는 사실을 알게 되었다. 이 사실은 In2O3기판을 사용하고 이의 표면거칠기를 열처리로 조절하므로써 역시 나노와이어의 성장을 촉진하는 방법을 찾아내었다. 또한 thermal evaporation공법은 source분말의 선택에 따라 다양한 소재를 제작가능하다는 결과를 제시하였다. 예를 들면 SiOx 층이 precoating된 chamber내에서 MgO 나노선을 합성하는 것과 동일한 조건으로 실험을 진행하면 Mg2SiO4 나노와이어가 형성된 것을 확인하였다. 또한 Sn과 MgB2 분말을 함께 적용할 경우 Sn tip을 가진 MgO 나노와이어를 얻을 수 있었다. 이는 Sn이 동시에 촉매의 역할을 하였기 때문일 것으로 추정된다. 한편 Sn과 Bi 혼합분말을 적용한 경우 Bi2Sn2O7 신소재 tip을 포함한 SnO2 나노와이어를 얻을 수 있었다. 이 경우 Bi원자가 적절한 촉매의 역할을 수행한 것으로 사료된다. Substrate의 가열공법에서는 Si wafer상에 각종 금속 즉 Au, Ag, Cu, Co, Mo, W, Pt, Pd등 초박막을 DC sputter 로 형성한후 annealing하는 기술을 사용하였다. 특기할 만한 것은 Co를 사용한 경우 나노와이어의 spring구조를 얻을 수 있었다는 점이다. MOCVD에 의하여는 Ga2O3및 Bi2O3 나노와이어를 비교적 저온에서 합성하였고 In2O3의 경우는 독특한 나노구조를 형성하였고 이의 결정학적 특성에 대하여 조사하였다.

• Journal of Electrochemical Science and Technology
• /
• v.10 no.2
• /
• pp.196-205
• /
• 2019

Ni-rich layered oxides $Li(Ni_xCo_yMn_z)O_2$ (x + y + z = 1) have been extensively studied in recent times owing to their high capacity and low cost and can possibly replace $LiCoO_2$ in the near future. However, these layered oxides suffer from problems related to the capacity fading, thermal stability, and safety at high voltages. In this study, we use surface coating as a strategy to improve the thermal stability at higher voltages. The uniform and conformal $Al_2O_3$ coating on prefabricated electrodes using atomic layer deposition significantly prevented surface degradation over prolonged cycling. Initial capacity of 190, 199, 188 and $166mAh\;g^{-1}$ is obtained for pristine, 2, 5 and 10 cycles of ALD coated samples at 0.2C and maintains 145, 158, 151 and $130mAh\;g^{-1}$ for high current rate of 2C in room temperature. The two-cycle $Al_2O_3$ modified cathode retained 75% of its capacity after 500 cycles at 5C with 0.05% capacity decay per cycle, compared with 46.5% retention for a pristine electrode, at an elevated temperature. Despite the insulating nature of the $Al_2O_3$ coating, a thin layer is sufficient to improve the capacity retention at a high temperature. The $Al_2O_3$ coating can prevent the detrimental surface reactions at a high temperature. Thus, the morphology of the active material is well-maintained even after extensive cycling, whereas the bare electrode undergoes severe degradation.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2009.06a
• /
• pp.129-130
• /
• 2009

The P/E characteristics of $HfO_2$ CTF memory capacitor with $SiO_2/HfO_2/Al_2O_3$(OHA) engineered tunnel barrier were investigated. After a growth of thermal oxide with a thickness of 2 nm, 1 nm $HfO_2$ and 3 $Al_2O_3$ layers were deposited by atomic layer deposition (ALD) system. The band offset was calculated by analysis of conduction mechanisms through Fowler-Nordheim (FN) plot and Direct Tunneling (DT) plot. Moreover the PIE characteristics of $HfO_2$ CTF memory capacitor with OHA tunnel barrier was presented.

• Proceedings of the Korean Vacuum Society Conference
• /
• 2010.08a
• /
• pp.196-197
• /
• 2010

NAND형 charge trap flash (CTF) non-volatile memory (NVM) 소자가 30nm node 이하로 고집적화 되면서, 기존의 SONOS형 CTF NVM의 tunnel barrier로 쓰이는 SiO2는 direct tunneling과 stress induced leakage current (SILC)등의 효과로 인해 data retention의 감소 등 물리적인 한계에 이르렀다. 이에 따라 개선된 retention과 빠른 쓰기/지우기 속도를 만족시키기 위해서 tunnel barrier engineering (TBE)가 제안되었다. TBE NVM은 tunnel layer의 전위장벽을 엔지니어드함으로써 낮은 전압에서 전계의 민감도를 향상 시켜 동일한 두께의 단일 SiO2 터널베리어 보다 빠른 쓰기/지우기 속도를 확보할 수 있다. 또한 최근에 각광받는 high-k 물질을 TBE NVM에 적용시키는 연구가 활발히 진행 중이다. 본 연구에서는 Si3N4와 HfAlO (HfO2 : Al2O3 = 1:3)을 적층시켜 staggered의 새로운 구조의 tunnel barrier Capacitor를 제작하여 전기적 특성을 후속 열처리 온도와 방법에 따라 평가하였다. 실험은 n-type Si (100) wafer를 RCA 클리닝 실시한 후 Low pressure chemical vapor deposition (LPCVD)를 이용하여 Si3N4 3 nm 증착 후, Atomic layer deposition (ALD)를 이용하여 HfAlO를 3 nm 증착하였다. 게이트 전극은 e-beam evaporation을 이용하여 Al를 150 nm 증착하였다. 후속 열처리는 수소가 2% 함유된 질소 분위기에서 $300^{\circ}C$와 $450^{\circ}C$에서 Forming gas annealing (FGA) 실시하였고 질소 분위기에서 $600^{\circ}C{\sim}1000^{\circ}C$까지 Rapid thermal annealing (RTA)을 각각 실시하였다. 전기적 특성 분석은 후속 열처리 공정의 온도와 열처리 방법에 따라 Current-voltage와 Capacitance-voltage 특성을 조사하였다.

• Journal of the Korean Vacuum Society
• /
• v.19 no.5
• /
• pp.385-390
• /
• 2010

We studied the optical characteristics of ZnO:Al and $Al_2O_3$ coated ZnO nanorods. When ZnO:Al is deposited around the undoped ZnO nanorods, thermal diffusion of Al into ZnO gives rise to decrease the binding energy of neutral donor bound exciton whereas an insulating Al2O3 is coated around ZnO, we found that semiconducor-insulator interface states play an important role in optical quenching.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.22 no.6
• /
• pp.466-468
• /
• 2009

The metal-insulator-silicon (MIS) capacitors with $SiO_2$ and high-k dielectrics ($HfO_2$, $Al_2O_3$) were fabricated, and the current-voltage characteristics were investigated. Especially, an effective barrier height between metal gate and dielectric was extracted by using Fowler-Nordheim (FN) plot and Direct Tunneling (DT) plot of quantum mechanical(QM) modeling. The calculated barrier heights of thermal $SiO_2$, ALD $SiO_2$, $HfO_2$ and $Al_2O_3$ are 3.35 eV, 0.6 eV, 1.75 eV, and 2.65 eV, respectively. Therefore, the performance of non-volatile memory devices can be improved by using engineered tunnel barrier which is considered effective barrier height of high-k materials.

• Proceedings of the Korean Vacuum Society Conference
• /
• 2012.02a
• /
• pp.154-154
• /
• 2012

Flexible complementary inverters based on thin-film transistors (TFTs) are important because they have low power consumption and high voltage gain compared to single type circuits. We have manufactured flexible complementary inverters using pentacene and amorphous indium gallium zinc oxide (IGZO) for the p-channel and n-channel, respectively. The circuits were fabricated on polyimide (PI) substrate. Firstly, a thin poly-4-vinyl phenol (PVP) layer was spin coated on PI substrate to make a smooth surface with rms surface roughness of 0.3 nm, which was required to grow high quality IGZO layers. Then, Ni gate electrode was deposited on the PVP layer by e-beam evaporator. 400-nm-thick PVP and 20-nm-thick ALD Al2O3 dielectric was deposited in sequence as a double gate dielectric layer for high flexibility and low leakage current. Then, IGZO and pentacene semiconductor layers were deposited by rf sputter and thermal evaporator, respectively, using shadow masks. Finally, Al and Au source/drain electrodes of 70 nm were respectively deposited on each semiconductor layer using shadow masks by thermal evaporator. The characteristics of TFTs and inverters were evaluated at different bending radii. The applied strain led to change in voltage transfer characteristics of complementary inverters as well as source-drain saturation current, field effect mobility and threshold voltage of TFTs. The switching threshold voltage of fabricated inverters was decreased with increasing bending radius, which is related to change in parameters of TFTs. Throughout the bending experiments, relationship between circuit performance and TFT characteristics under mechanical deformation could be elucidated.