• Biomolecules & Therapeutics
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• v.17 no.2
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• pp.151-155
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• 2009

Hepatitis C virus (HCV) has genetic diversity like most of RNA viruses. HCV major genotypes are classified into several subtypes which are further divided into quasispecies having, genetically different but closely related variants. The HCV core that is a nucleocapsid protein located at the amino terminus of the viral polyprotein is relatively a conserved protein among the HCV isolates and thus it has been one of plausible targets for anti-HCV drug development. However, different quasispecies of HCV core gene have also been found. In this study, we compared the expression level of core protein between two different quasispecies of HCV genotype 1b. Our data demonstrate that a little differences of amino acid sequence lead to substantial difference of expression level. It might be another important reason of different pathogenesis among HCV infected patients.

• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.659-662
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• 2005

A parameterized FFT/IFFT core generator (PFFT_CoreGen) is designed, which can be used as an essential IP (Intellectual Property) in various OFDM modem designs. The PFFT_CoreGen generates Verilog-HDL models of FFT cores in the range of 64 ${\sim}$ 2048-point. To optimize the performance of the generated FFT cores, the PFFT_CoreGen can select the word-length of input data, internal data and twiddle factors in the range of 8-b ${\sim}$ 24-b. Some design techniques for low-power design are considered from algorithm level to circuit level.

• IEMEK Journal of Embedded Systems and Applications
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• v.7 no.5
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• pp.277-284
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• 2012

To meet the usage of discrete wavelet transform (DWT) on potable devices, this paper implements 2-level DWT using a reference many-core processor architecture and determine the optimal many-core processor. To explore the optimal many-core processor, we evaluate the impacts of a data-per-processing element ratio that is defined as the amount of data mapped directly to each processing element (PE) on system performance, energy efficiency, and area efficiency, respectively. This paper utilized five PE configurations (PEs=16, 64, 256, 1,024, and 4,096) that were implemented in 130nm CMOS technology with a 720MHz clock frequency. Experimental results indicated that maximum energy and area efficiencies were achieved at PEs=1,024. However, the system area must be limited 140mm2 and the power should not exceed 3 watts in order to implement 2-level DWT on portable devices. When we consider these restrictions, the most reasonable energy and area efficiencies were achieved at PEs=256.

• Journal of the Architectural Institute of Korea Structure & Construction
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• v.35 no.6
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• pp.101-109
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• 2019

The purpose of this study is to improve a general Top-Down construction process for superstructure construction period reduction. In a general Top-Down construction sequence, the ground floor slab is set up first. Subsequently, 1st basement level construction including core walls is constructed. Initiation of the ground level superstructure gets waited until then. In this study, removable deck plate installation on the bottom of the core walls of ground level is preceding the concrete casting, therefore, ground level superstructure construction is able to get started earlier. Up to first typical floor concrete casting, total of seventy-two working(calendar) days will be resulted in a reduction from the total construction periods.

• Journal of the Korea Institute of Military Science and Technology
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• v.19 no.6
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• pp.789-796
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• 2016

In the Core Technology R&D of the defence area, the development of the related core element technology could be the foundation to develop advanced weapon system in the future. But it might make various problems if you can not accurately define the TRL of the element technology. In other words, if the technology is not sufficiently mature and then the project starts, it might require an increase in the development period and additional cost. Finally the system will be in an incomplete state and result in user dissatisfaction and the project failure. Therefore it is a very important task to properly assess the TRL for a successful project. In this study, We propose the method for risk management of core technology R&D project of the defence area using the QFD process with degree of difficulty and technology readiness level. It is also presented the process to determine the risk level using TRL and Degree of difficulty. Finally We apply this method to UGV system for verifying the result of this study.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2010.05a
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• pp.19-20
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• 2010

• The KSFM Journal of Fluid Machinery
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• v.5 no.1 s.14
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• pp.49-54
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• 2002

HANARO, 30 MW of research reactor, was installed at the depth of 13m in an open pool. The $90\%$ of primary coolant was designed to pass through the core and to remove the reaction heat of the cote. The rest, $10\%$, of the primary coolant was designed to bypass the core. And the reactor coolant through and bypass the core was inhaled at the top of chimney by the coolant pump to prevent the radiated gas from being lifted to the top of reactor pool. But, the part of core bypass coolant was not inhaled by the reactor coolant pump and reached at the top of reactor pool by natural convection, and increased the radiation lovel on the top of reactor pool. To reduce the radiation level by protecting the natural convection of the core bypass flow, the hot water layer (HWL, hereinafter) was installed with the depth of 1.2 m from the top of reactor pool. As the HWL was normally operated, the radiation level was reduced to five percent ($5\%$) in comparing with that before the installation of the HWL. When HANARO was operated at a higher temperature than the normal temperature of the HWL by operating the standby heater, it was found that the radiation level was more reduced than that before operation. To verify the reason, the heat loss of the HWL was calculated by Visual Basic Program. It was confirmed through the results that the larger the temperature difference between the HWL and reactor hall was, the more the evaporation loss increased. And it was verified that the radiation level above was reduced mote safely by increasing the capacity of heater.

• Journal of KIISE:Computing Practices and Letters
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• v.16 no.8
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• pp.863-867
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• 2010

Multi-core processors are becoming increasingly popular. As they are widely adopted in embedded systems as well as desktop PC's, many multimedia applications are being parallelized on multi-core platforms. However, it is difficult to parallelize applications with inherent data dependencies such as encryption algorithms for multimedia data. In order to overcome this limit, we propose a technique to overlap computation and communication using an otherwise idle core in this paper. In particular, we interpret the problem of multimedia computation and communication as a pipeline design problem at the application program level, and derive an optimal number of stages in the pipeline.

• Journal of Satellite, Information and Communications
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• v.9 no.4
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• pp.73-76
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• 2014

With the increasing popularity of multi-core processors, they have been adopted even in embedded systems. Under this circumstance many multimedia applications can be parallelized on multi-core platforms because they usually require heavy computations and extensive memory accesses. This paper proposes an efficient thread-level parallel implementation for color space conversion on multi-core CPU. Thread-level parallelism has been becoming very useful parallel processing paradigm especially on shared memory computing systems. In this work, it is exploited by allocating different input pixels to each thread for concurrent loop executions. For the performance evaluation, this paper evaluate the performace improvements for color conversion on multi-core processors based on the processing speed comparison between its serial implementation and parallel ones. The results shows that thread-level parallel implementations show the overall similar ratios of performance improvements regardless of different multi-cores.

• Steel and Composite Structures
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• v.38 no.6
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• pp.671-690
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• 2021

Seismic responses of RC core wall with two outriggers are investigated in this study. In the models analyzed here, one of the outriggers is fixed at the top of the building and the second is placed at different levels along the height of the system. Each of the systems resulting from the placement of the outrigger at different locations is designed according to the prescriptive codes. The location of the outrigger changes along the height. Linear design of all the structures is accomplished by using prescriptive codes. Buckling restrained braces (BRBs) are used in the outriggers and forward directivity near fault and far fault earthquake record sets are used at maximum considered earthquake (MCE) level. Results from nonlinear time history analysis demonstrate that BRB outriggers can change the seismic responses like force distribution and deformation demand of the RC core-walls over the height and lead to the new plastic hinge arrangement over the core-wall height. Plasticity extension in the RC core wall occurs at the base as well as adjacent to the outrigger levels. Considering the maximum inter-story drift ratio (IDR) demand as an engineering parameter, the best location for the second outrigger is at 0.75H, in which the maximum IDR at the region upper the second outrigger level is approximately equal to the corresponding value in the lower region.