• Proceedings of the Korean Information Science Society Conference
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• 2004.04b
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• pp.427-429
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• 2004

잘 설계된 모든 객체지향 구조들은 패턴들로 가득 차 있다는 점에서 볼 때, 디자인 패턴은 상당히 유용하다. 특히 정확성. 강건성, 유연성, 재사용성, 효율성 측면에서 볼 때, 디자인 패턴은 충분히 가치가 있다. 이 논문에서는 디자인 패턴을 사용한 소프트웨어에서 테스트 가능성은 어떻게 달라지는지를 분석하고자 한다. 테스트 가능성을 측정하는 메트릭을 이용하여, 패턴이 적용된 소프트웨어와 적용되지 않은 소프트웨어에서의 메트릭을 분석한다. 측정된 값은 디자인 패턴을 사용하지 않은 소프트웨어에 비해, 사용한 소프트웨어에서 몇몇 메트릭이 낮은 값을 보였다 이것은 디자인 패턴을 적용하는 것이 오류의 가능성이나 테스트 케이스의 수를 줄여 준다는 것을 의미한다. 또한 어떤 디자인 패턴이 적용되었는지를 알고 있을 때 그 디자인 패턴에 맞는 테스트 케이스가 무엇인지 분석하였다.

• Communications for Statistical Applications and Methods
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• v.28 no.3
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• pp.307-314
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• 2021

We showed that any missing mechanism is reproduced by EMAR or MNAR with equal fit for observed likelihood if there are non-negative solutions of maximum likelihood equations. This is a generalization of Molenberghs et al. (2008) and Jeon et al. (2019). Nonetheless, as MCAR becomes a nested model of MNAR, a natural question is whether or not MNAR and MCAR are testable by using the well-known three statistics, LR (Likelihood ratio), Wald, and Score test statistics. Through simulation studies, we compared these three statistics. We investigated to what extent the boundary solution affect tesing MCAR against MNAR, which is the only testable pair of missing mechanisms based on observed likelihood. We showed that all three statistics are useful as long as the boundary proximity is far from 1.

• Proceedings of the Korea Information Processing Society Conference
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• 2010.11a
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• pp.340-343
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• 2010

스마트폰 어플리케이션은 소프트웨어의 평가를 구매자가 쉽게 확인 및 작성할 수 있어 품질이 매출에 직접적으로 영향을 끼쳐 소프트웨어의 품질을 향상시키기 위해서 테스트가 요구된다. 하지만 기존의 스마트폰 어플리케이션은 테스트 용이성을 고려하지 않고 개발되어 테스트를 위해 많은 비용이 증가한다. 본 논문은 이 문제를 해결하고자 소프트웨어 설계 단계에서 모델변환을 적용하여 테스트 용이성을 향상 시키는 방법을 제안한다. 대상 모델은 UML의 클래스 다이어그램이고 테스트 용이성 측정을 위해서 Binder방법을 사용한다. 적용사례로 안드로이드 기반의 소프트웨어인 SnakePlus를 구현하고, 이를 대상으로 설계 모델을 모델변환을 하여 테스트 용이성을 향상 시킨다.

• Proceedings of the Korea Information Processing Society Conference
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• 2010.11a
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• pp.318-321
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• 2010

임베디드 소프트웨어를 테스트하고 디버깅하려면 기능 분석, 프로세스 추적, 메모리 디버깅 등 다양한 기술들이 존재한다. 하지만 테스터가 임베디드 시스템 내부의 컴포넌트들의 사이에 결함을 발견하고 그 위치를 찾아야 하는 경우, 디버깅 기술과 도구만으로는 한계가 있다. 만약 테스터가 테스트 도구를 이용할 경우 이런 단점을 보완할 수 있지만 다양한 임베디드 시스템 환경에서는 테스트 환경만을 구축하는 데도 많은 노력과 시간이 소요된다. 따라서 이러한 문제 해결하기 위하여 본 논문에서는 관점 지향 프로그래밍(Aspect-Oriented Programming)을 사용한 후크(Hook) 개념을 적용하여 새로운 테스팅 아키텍처를 제안한다.

• International Journal of Computer Science & Network Security
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• v.23 no.1
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• pp.103-111
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• 2023

Implementing conventional DFT solution for arrays of DNN accelerators having large number of processing elements (PEs), without considering architectural characteristics of PEs may incur overwhelming test overheads. Recent DFT based techniques have utilized the homogeneity and dataflow of arrays at PE-level and Core-level for obtaining reduction in; test pattern volume, test time, test power and ATPG runtime. This paper reviews these contemporary test solutions for ASIC based DNN accelerators. Mainly, the proposed test architectures, pattern application method with their objectives are reviewed. It is observed that exploitation of architectural characteristic such as homogeneity and dataflow of PEs/ arrays results in reduced test overheads.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.19 no.3
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• pp.401-417
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• 1994

In this paper, a new testable design technique for domino CMOS circuits is proposed to detect stuck-at(s-at), stuck-open(s-op) and stuck-on(s-on) faults in the circuits by observing logic test reponses. The proposed technique adds one pMOS transistor per domino CMOS gate for s-op and s-on faults testing of nMOS transistors and one nMOS transistors and one nMOS transistor per domino gate or multilevel circuit to detect s-on faults in pMOS transistors of inverters in the circuit. The extra transistors enable the proposed testable circuit to operate like a pseudo static nMOS circuit while testing nMOS transistors in domino CMOS circuits. Therefore, the two=phase operation of a precharge phase and a evaluation phase is not needed to keep the domino CMOS circuit from malfunctionong due to circuit delays in the test mode, which reduces the testing time and the complexity of test generation. Most faults of th transistors in the proposed testable domino CMOS circuit can be detected by single test patterns. The use of single test patterns makes the testing of the proposed testable domino CMOS circuit free from path delays, timing skews, chage sharing and glitches. In the proposed design, the testing of the faults which, require test sequences also becomes free from test invalidation. The conventional automatic test pattern generators(ATPG) can be used for generating test patterns to detect faults in the circuits.

• ETRI Journal
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• v.29 no.3
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• pp.371-380
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• 2007

This paper proposes a new automatic compensation network (ACN) for a system-on-chip (SoC) transceiver. We built a 5 GHz low noise amplifier (LNA) with an on-chip ACN using 0.18 ${\mu}m$ SiGe technology. This network is extremely useful for today's radio frequency (RF) integrated circuit devices in a complete RF transceiver environment. The network comprises an RF design-for-testability (DFT) circuit, capacitor mirror banks, and a digital signal processor. The RF DFT circuit consists of a test amplifier and RF peak detectors. The RF DFT circuit helps the network to provide DC output voltages, which makes the compensation network automatic. The proposed technique utilizes output DC voltage measurements and these measured values are translated into the LNA specifications such as input impedance, gain, and noise figure using the developed mathematical equations. The ACN automatically adjusts the performance of the 5 GHz LNA with the processor in the SoC transceiver when the LNA goes out of the normal range of operation. The ACN compensates abnormal operation due to unusual thermal variation or unusual process variation. The ACN is simple, inexpensive and suitable for a complete RF transceiver environment.

• Journal of KIISE:Computer Systems and Theory
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• v.28 no.10
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• pp.541-547
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• 2001

Testing a core-based designed chip requires a full isolation ring to provide fro core test data access to each core. A partial isolation ring replaces the full isolation ring reducing total isolation ring size surrounding. This paper proposes an efficient method to reduce the size of the partial isolation ring and shorten the time to acquire the final solution. For this, a reasonable ordering technique according to testability is introduced and a sorting technique is adopted to reduce the total solution time. Experimental results show that the proposed method can be useful in practice.

• ETRI Journal
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• v.30 no.3
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• pp.412-420
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• 2008

A new scan partition architecture to reduce both the average and peak power dissipation during scan testing is proposed for low-power embedded systems. In scan-based testing, due to the extremely high switching activity during the scan shift operation, the power consumption increases considerably. In addition, the reduced correlation between consecutive test patterns may increase the power consumed during the capture cycle. In the proposed architecture, only a subset of scan cells is loaded with test stimulus and captured with test responses by freezing the remaining scan cells according to the spectrum of unspecified bits in the test cubes. To optimize the proposed process, a novel graph-based heuristic to partition the scan chain into several segments and a technique to increase the number of don't cares in the given test set have been developed. Experimental results on large ISCAS89 benchmark circuits show that the proposed technique, compared to the traditional full scan scheme, can reduce both the average switching activities and the average peak switching activities by 92.37% and 41.21%, respectively.

• Proceedings of the KSRS Conference
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• 2005.10a
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• pp.586-588
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• 2005

The MSC (Multi Spectral Camera) system is a remote sensing payload to obtain high resolution ground image. This system uses lossy image compression method for &Direct mission& that transmit whole image during one contact. But some image degradation occurred especially at high compression ratio. To reduce this degradation, the MSC uses NUC (Non-uniformity Correction) Unit. This unit correct CCD (Charge Coupled Device)'s high-frequency non-uniformity. So high frequency contents of image can be minimized and whole system SNR can be maximized. But NUC has some disadvantage either. It decreases entire system reliability by adding one electronic system. Adding NUC also led to difficulty of electronic design, assembly and testability. In this paper, the comparison is performed between on-orbit non-uniform correction and on ground correction. by evaluating NUC advantage for the point of view of image quality. Using real MSC parameter and proper model, considerable reference point for the system design came to possible.