• Journal of the Korean Institute of Telematics and Electronics
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• v.27 no.11
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• pp.42-48
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• 1990

In this paper robust test generation for stuck-open faults in CMOS circuits is proposed. By obtaining initialization patterns and test patterns using the relationship of bit position and Hamming weight among input vectors for CMOS circuit test generation time for stuck-open faults can be reduced, and the problem of input transition skew which make fault detection difficult is solved, and the number of test sequences are minimized. Also the number of test sequences is reduced by arranging test sequences using Hamming distance between initialization patterns and test patterns for circuit.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.6
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• pp.72-84
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• 2000

The test patterns for path delay faults consist of two patterns. So in order to test the delay faults, a new weight generation algorithm that is different from the weight generation algorithm for stuck-at faults must be applied. When deterministic test patterns for weight calculation are used, the deterministic test patterns must be divided into several subsets, so that Hamming distances between patterns are not too long. But this method makes the number of weight sets too large in delay testing, and may generate inaccurate weights. In this pater, we perform fault simulation without pattern partition. Experimental results for ISCAS 89 benchmark circuits prove the effectiveness of the new weight generation algorithm proposed in this paper.

• Journal of the Korean Institute of Telematics and Electronics
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• v.26 no.3
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• pp.40-49
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• 1989

A variable-state block interference channel model is presented which matches asynchronous multiple-access slow frequency-hopped spread-spectrum systems which suffer from bursts of interference of variable duration. For variable-state block interference channels test pattern techniques combined with interleaving are presented from which the decoder obtain side information about channel states. By examining test patterns the decoder estimates which parts of data blocks are affected by interference and regards the parts of blocks affected by interference as erasures. Since the presence of test patterns reduces the number of bits for data transmission, test patterns are not useful for variable-state block interference channels for small hit probability, It is shown that test patterns increase the capacities of variable-state block interference channels for large hit probability. It is also shown that test patterns provide a almost full side information about channel states for certain values of parameters.

• Journal of the Korean Home Economics Association
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• v.39 no.12
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• pp.177-188
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• 2001

The purpose of this study is to investigate the fitness according to drafting method of the block patterns for women in Korea. The major findings of this study are as follows: 1. According to each sensory test of the frontal view, back view, side view and silhouette Block Pattern I is the best of them in summation of the sensory tests score. Block, Pattern D and I have good shape too. However the best block Pattern D shows good score in evaluation of overall fitness and silhouette. 2. Most of block patterns, which show high scores in sensory tests, are the Compromise Method taking merits of the Proportional Method and Short Measure Method among the Pattern Drafting Methods. Box-shape patterns show low score in the sensory tests. 3. Regarding to the number of measurement, the patterns of the Compromise Method using 6-8 measurements seem to be optimal. In degree of fitness, loose fit type basic patterns are better than other patterns from a viewpoint of the total satisfaction.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.32B no.5
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• pp.661-670
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• 1995

This paper presents a fast massively parallel automatic test pattern generator for digital combinational logic circuits using neural networks. Automatic test pattern generation neural network(ATPGNN) evolves its state to a stable local minima by exchanging messages among neural network modules. In preprocessing phase, we calculate the essential assignments for the stuck-at faults in fault list by adopting dominator concept. It makes more neurons be fixed and the system speed up. Consequently. fast test pattern generation is achieved. Test patterns for stuck-open faults are generated through getting initialization patterns for the obtained stuck-at faults in the corresponding ATPGNN.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.30A no.1
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• pp.8-15
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• 1993

A concrete disign of memory circuit is presented aiming at the application of sliding diagonal test patterns. A modification of sliding diagonal test pattern includes the complexity reduction from O(n$^{32}$) to O(n) using parallel test memory concept. The control circuit design was based on delay-element, and verified via logic and circuit simulation. Area overhead was evaluated based on physical layout using a 0.7 micron design rule resulting in about 1% area increase for a typical 16Mbit DRAM.

• Journal of Electrical Engineering and Technology
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• v.8 no.3
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• pp.603-609
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• 2013

In this paper, we describe the analysis of inkjet-printed silver (Ag) patterns on epoxy-coated substrates according to several reliability evaluation test method guidelines for conventional printed circuit boards (PCB). To prepare patterns for the reliability analysis, various regular test patterns were created by Ag inkjet printing on flame retardant 4 (FR4) and polyimide (PI) substrates coated with epoxy for each test method. We coated the substrates with an epoxy primer layer to control the surface energy during printing of the patterns. The contact angle of the ink to the coated epoxy primer was $69^{\circ}$, and its surface energy was 18.6 $mJ/m^2$. Also, the substrate temperature was set at $70^{\circ}C$. We were able to obtain continuous line patterns by inkjet printing with a droplet spacing of $60{\mu}m$. The reliability evaluation tests included the dielectric withstanding voltage, adhesive strength, thermal shock, pressure cooker, bending, uniformity of line-width and spacing, and high-frequency transmission loss tests.

• Journal of the Korean Institute of Telematics and Electronics
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• v.14 no.6
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• pp.10-15
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• 1977

This paper proposes a simple and systematic method for the generation of the fault detection test sets for the combinational logic networks. Based on tile path sensitizing concept, the test patterns for the primary input gates of the network are defined, and then it is shown that, arranging these predefined test patterns according to the path sensitizing characteristics of the given network sturctures, the minimal complete test sets for the fan-out free combinational networks can be found easily. It is also shown that, taking into account the fan-out paths sensitizing compatibility, the proposed method can be extended to the irredundant reconvergent fan-out networks.

• The Research Journal of the Costume Culture
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• v.12 no.2
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• pp.290-299
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• 2004

The purpose of this study is to testify the pattern making method to develop the men's basic bodice pattern using 3-dimensional body scan data. The experimental patterns were made by adding wearing ease on flattened body scan data and tracing the outlines of it. The experimental bodice pattern were composed of front, back, and side panels. To compare the difference between the experimental pattern and traditional pattern, two pattern making methods were compared. Two sets of basic bodice patterns were made for each of the 10 male subjects: a set of pattern was made by experimental method and the other set was made by Bunka pattern making method. The experimental and traditional patterns were measured at 13 dimensions. The results show that there was a difference between the experimental patterns and traditional patterns at the front length, back length, front width, front neck width, back neck width, and back neck depth. The fit was also compared for both patterns. The results of the fit test show that the experimental patterns were superior to the traditional patterns at the fit of neck, shoulder, and armhole. The experimental pattern making method was expected to be useful for mass customization.

• Journal of Fashion Business
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• v.18 no.6
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• pp.116-136
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• 2014

The purpose of this study was to select patterns for slim fit pants, for the following main research, to develop new pants patterns that are suitable and preferable for men in their 20s. We compared and analyzed the patterns of which are currently in the market. We compared 10 different slim pants pattern drafting and analyzed their differences. Then, we examined their appearances and functionalities thru a male model test fitting 10 different samples of the pants. The conclusions of the research results were as follows. We listed the patterns in the following order based on the numbers of items each pattern has, which are statistically considerable for the evaluation to the optimum satisfactory level among the total of 35 testing categories: J > B=I > F=H > A > C=G > D > E. In the functionality test of the pants, we found that it was too tight around the waist and abdomen area with Pattern D, where-as it was too loose around the waist with Pattern C:,-, yet, both of the patterns indicated that it is a good fit in over-all. Therefore, we chose Pattern E, D, C, and G as the existing pants patterns that could be used for further research and for educational purposes to develop a slim pants pattern for men in their 20s.