• Journal of KIISE:Software and Applications
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• v.32 no.7
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• pp.592-600
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• 2005

Systematically extracting the test patterns of hot spots in an object-oriented software framework is a prerequisite for thoroughly testing the framework's functionality in a variety of contexts in which the framework is extended for reuse. This paper proposes a method for analyzing the design patterns and extracting the test patterns from the interaction test patterns of hot spots in an object-oriented framework. Based on the design pattern of the framework's hot spot, our method captures the object behavior allowed in that hot spot by means of statecharts, which are then used to generate the interaction test patterns and test cases. The generated test patterns and test cases can be applied repeatedly to applications which are built from extending the framework.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.12A
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• pp.2008-2014
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• 1999

IDDQ testing is an effective testing method to detect various physical defects occurred in CMOS circuits. In this paper, we consider intra-gate shorts within circuit under test and implement IDDQ test pattern generator to find test patterns which detect considered defects. In order to generate test patterns, gate test vectors which detect all intra-gate shorts have to be found by type of gates. Random test sets of 10,000 patterns are applied to circuit under test. If an applied pattern generates a required test vector of any gate, the pattern is saved as an available test pattern. When applied patterns generate all test vectors of all gats or 10,000 patterns are applied to circuit under test, procedure of test pattern generation is terminated. Experimental results for ISCAS'85 bench mark circuits show that its efficiency is more enhanced than that obtained by previously proposed methods.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.29B no.9
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• pp.1-7
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• 1992

This paper proposes a built-in self-test tchnique for CMOS circuits. To detect a stuck-open fault in CMOS circuits, two consequent test patterns is required. The ordered pairs of test patterns for stuck-open faults are generated by feedback shift registers of extended length. A nonlinear feedback shift register is designed by the merging method and reordering algorithms of test patterns proposed in this paper. And a new multifunctional BILBO (Built-In Logic Block Observer) is designed to perform both test pattern generation and signature analysis efficiently.

• Journal of Advanced Marine Engineering and Technology
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• v.22 no.5
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• pp.687-692
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• 1998

Test pattern generation is one of most difficult problems encountered in automating the design of logic circuits. The goal is to obtain the highest fault coverage with the minimum number of test patterns for a given circuit and fault set. although there have been many deterministic algorithms and heuristics the problem is still highly complex and time-consuming. Therefore new approach-es are needed to augment the existing techniques. This paper considers the problem of test pattern improvement for combinational circuits as a restricted subproblem of the test pattern generation. The problem is to maximize the fault coverage with a fixed number of test patterns for a given cir-cuit and fault set. We propose a new approach by use of a genetic algorithm. In this approach the genetic algorithm evolves test patterns to improve their fault coverage. A fault simulation is used to compute the fault coverage of the test patterns Experimental results show that the genetic algorithm based approach can achieve higher fault coverages than traditional techniques for most combinational circuits. Another advantage of the approach is that the genetic algorithm needs no detailed knowledge of faulty circuits under test.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.32A no.9
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• pp.114-120
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• 1995

It is important to test the various kinds of interconnect faults between chips on a card/module. When boundary scan design techniques are adopted, the chip to chip interconnection test generation and application of test patterns is greatly simplified. Various test generation algorithms have been developed for interconnect faults. A new interconnect test generation algorithm is introduced. It reduces the number of test patterns by half over present techniques. It also guarantees the complete diagnosis of mutiple interconnect faults.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.9
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• pp.38-48
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• 1998

Generating test patterns for asynchronous sequential circuits remains to be a very difficult problem. There are few algorithms for this problem, and previous works cut feedback loops, and insert synchronous flip-flops in the feedback loops during ATPG. The conventional algorithms are similar to the algorithms for synchronous sequential circuits. This means that the conventional algorithms generate test patterns by modeling asynchronous sequential circuits as synchronous sequential circuits. So, test patterns generated by those algorithms nay not detect target faults when the test patterns are applied to the asynchronous sequential circuit under test. In this paper an algorithm is presented to generate test patterns for asynchronous sequential circuits. Test patterns generated by the algorithm can detect target faults for asynchronous sequential circuits with the minimal possibility of critical race problem and oscillation. And it is guaranteed that the test patterns generated by the algorithm will detect target faults.

• The Transactions of the Korea Information Processing Society
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• v.5 no.9
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• pp.2369-2377
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• 1998

Fault simulators are used to evaluate the quality of a test pattern generated. So far, most fault simulators did not handle bus conflicts properly. We analyzed . all possible bus conflicts when test patterns are applied to a circuit with bus structure and categorized bus conflicts into various types. Also. we proposed an efficient method to identify various types of bus conflicts. The fault simulator which employs the proposed method can evaluate the quality of test patterns generated and also can avoid destruction of bus drivers due to bus conflicts hy warning the use of test patterns which cause bus conflicts. The proposed method can also be incorperated into a test pattern generator so that it can generate conflict-free test patterns.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.8 s.350
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• pp.27-34
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• 2006

During Built-In Self-Test(BIST), The set of patterns generated by a pseudo-random pattern generator may not provide sufficiently high fault coverage and many patterns were undetected fault. In order to reduce the test time, we can remove useless patterns or change from them to useful patterns. In this paper, we reseed modify the pseudo-random and use an additional bit flag to improve test length and achieve high fault coverage. the fat that a random tset set contains useless patterns, so we present a technique, including both reseeding and bit modifying to remove useless patterns or change from them to useful patterns, and when the patterns change, we choose number of different less bit, leading to very short test length. the technique we present is applicable for single-stuck-at faults. the seeds we use are deterministic so 100% faults coverage can be achieve.

• Journal of The Korean Association For Science Education
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• v.14 no.2
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• pp.111-122
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• 1994

This study tried to find the effect to the representation patterns of science concepts upon the momentum effect. The previous studies showed that the momentum effect is influenced by students' cognitive levels and the abstractness of test items. The representation patterns of science concepts are divided into 4 different types: quantitative and qualitative, verbal and image. The research method used in this study is time series design. The period is 50 days. The period is divided into "pre-lest", "intervention-test", "post-test". Pre-test period is 5 days and in this period class instruction does not exist. Intervention-lest period is 30 days and in this period class instruction exist. Post-test period is 15 days and in this period class instruction does not exist. The results showed longer momentum effect on the image-qualitative representation pattern than the other representation patterns. Qualitative concepts is formed better than quantitative. Momentum effects is not artifact but the essential characteristics of science study.

• Transactions of the Korean Society of Automotive Engineers
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• v.9 no.1
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• pp.131-138
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• 2001

The performance analysis of an electronic equipment test is very complicate due to the variety o vehicles. In this study, automatic design system for the electronic equipment test has been carried out using the standard load patterns. For the test, standard signal patterns for each item are modeled. The test items can be decided by the user by means of these patterns. Also, engineering software modules are developed and proved to be very efficient for analyzing the test results statistically. Experiments are performed for the test system in the vehicle assembly line. By analyzing the test results, it is found that bad samples can be detected without failure. Also, the engineering software modules provide an analytical tool for the automation of the test process.