• Journal of IKEEE
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• v.24 no.1
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• pp.25-32
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• 2020

In this paper, we propose an image generator for OLED panel test that can compensate for color coordinates and luminance by using panel defect inspection and optical measurement while displaying images on OLED panel. The proposed image generator consists of two processes: the image generation process and the process of compensating color coordinates and luminance using optical measurement. In the image generating process, the panel is set to receive the panel information to drive the panel, and the image is output by adjusting the output setting of the image generator according to the panel information. The output form of the image is configured by digital RGB method. The pattern generation algorithm inside the image generator outputs color and gray image data by transmitting color data to a 24-bit data line based on a synchronization signal according to the resolution of the panel. The process of compensating color coordinates and luminance using optical measurement outputs an image to an OLED panel in an image generator, and compensates for a portion where color coordinates and luminance data measured by an optical module differ from reference data. To evaluate the accuracy of the image generator for the OLED panel test proposed in this paper, Xilinx's Spartan 6 series XC6SLX25-FG484 FPGA was used and the design tool was ISE 14.5. The output of the image generation process was confirmed that the target setting value and the simulation result value for the digital RGB output using the oscilloscope matched. Compensating the color coordinates and luminance using optical measurements showed accuracy within the error rate suggested by the panel manufacturer.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.9
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• pp.53-60
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• 1997

In this paper, an efficient BILBO(named EBILBO) is proposed for batch testing application when a BIST (built-in self test) circuit is implemented on ASIC. In a large and complex circuit, the proposed algorithm of batch testing has one pin-count that can easily control 4 test modes in the normal speed of circuit operation. For the implementation of the BIST cifcuit, the test patern needed is generated by PRTPG(pseudo-random test pattern generator) and the ouput is observed by proposed algorithm is easily modified, such as the modelling of test pattern genration, signature EBILBO area and performance of the implemented BIST are evaluated using ISCAS89 benchmark circuits. As a resutl, in a circuit above 600 gates, it is confirmed that test patterns are genrated flexibly about 500K as EBILBO area is 59%, and the range of fault coverage is from 88.3% to 100%. And the optimized operation frequency of EBILBO designed and the area are 50MHz and 150K respectively. On the BIST circit of the proposed batch testing, the test mode of EBILBO is able to execute as realtime that has te number of s$\^$+/n$\^$+/(2s/2p-1) clocks simultaneously with the normal mode of circuit operation. Also the proposed algorithm is made of the library with VHDL coding thus, it will be widely applied to DFT (design for testability) that satisfies the design and test field.

• Proceedings of the KSME Conference
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• 2003.04a
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• pp.304-309
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• 2003

In this study, natural flaws in welding parts are classified using the signal pattern classification method. The storage digital oscilloscope including FFT function and enveloped waveform generator is used and the signal pattern recognition procedure is made up the digital signal processing, feature extraction, feature selection and classifier design. It is composed with and discussed using the distance classifier that is based on euclidean distance the empirical Bayesian classifier. Feature extraction is performed using the class-mean scatter criteria. The signal pattern classification method is applied to the signal pattern recognition of natural flaws.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.33 no.1
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• pp.62-68
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• 2005

An injector for fuel rich gas generator was designed and experimentally investigated. Five variations of F-O-F triplet impinging type injector were tested to evaluate spray characteristics with kerosene/water simulant propellant. Test was focused to find the effect of design variables of impinging angle, and impinging distance, on the atomization performance. A mixing efficiency is used to compare droplet distribution and local O/F ratio of each injector in the range of momentum ratio of 0.2~1.3. Test results shows the max value of mixing efficiency locates about the 0.8 in momentum ratio. And the injector with an impinging angle of 45 degree and impinging distance of 6mm shows the very good performance result suitable for fuel rich gas generator. A combustion test will be also conducted with selected injector to verify the spray pattern and mixing efficiency.

• The Transactions of the Korea Information Processing Society
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• v.5 no.9
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• pp.2369-2377
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• 1998

Fault simulators are used to evaluate the quality of a test pattern generated. So far, most fault simulators did not handle bus conflicts properly. We analyzed . all possible bus conflicts when test patterns are applied to a circuit with bus structure and categorized bus conflicts into various types. Also. we proposed an efficient method to identify various types of bus conflicts. The fault simulator which employs the proposed method can evaluate the quality of test patterns generated and also can avoid destruction of bus drivers due to bus conflicts hy warning the use of test patterns which cause bus conflicts. The proposed method can also be incorperated into a test pattern generator so that it can generate conflict-free test patterns.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.20 no.10
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• pp.172-177
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• 2006

This paper presents a method to improve reliability considering dispersed generator(DG) installation and interruption cost with load types. It is used to the different interruption costs with load pattern of daily peak load. The objective functions such as power losses cost operation cost of DG, power buy cost and interruption cost are minimized for reliability improvement and efficient operation. The several indices for reliability evaluation are improved by dispersed generator installation. The proposed method is applied to IEEE 13 bus test systems to demonstrate its effectiveness.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.935-938
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• 1999

메모리 테스트는 Built-In Self Test(BIST)와 같이 메모리에 내장된 회로를 통하여 자체 점검하는 방법과 테스터를 통하여 생성된 패턴을 주입하는 방법이 있다. 테스트 패턴 생성방법으로는 각각의 고장모델에 대한 테스트 패턴을 deterministic하게 생성해주는 방법과 Pseudo Random Pattern Generator(PRPG)를 이용하여 생성하는 경우로 구분할 수 있다. 본 연구에서는 PRPG를 패턴 생성기로 사용하여 여러 가지 메모리의 결함을 대표한다고 볼 수 있는 Static 및 Dynamic Neighborhood Pattern Sensitive Fault(NPSF) 등 다양한 종류의 고장을 점검할 수 있도록 메모리 BIST를 구성하였다. 기존의 Linear Feedback Shift Register(LFSR)보다 본 연구에서 제안하는 Linear Hybrid Cellular Automata(LHCA)를 이용한 PRPG가 높고 안정된 고장 점검도를 나타내었다.

• Proceedings of the KIEE Conference
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• 2009.07a
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• pp.91_92
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• 2009

As the increasing integrity of VLSI, the BIST(Built-In Self Test) is used as an effective method to test chips. Generally the pseudo-random test pattern generation is used for BIST. But it requires too many test patterns when there exist random resistant faults. Therefore we propose a mixed test scheme which applies to the circuit under test, a deterministic test sequence followed by a pseudo-random one. This scheme allows the maximum fault coverage detection to be achieved, furthermore the silicon area overhead of the mixed hardware generator can be reduced.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.60 no.4
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• pp.796-800
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• 2011

As the increasing integrity of VLSI, the BIST(Built-In Self Test) is used as an effective method to test chips. Generally the pseudo-random test pattern generation is used for BIST. But it requires too many test patterns when there exist random resistant faults. Therefore we propose a mixed test scheme which applies to the circuit under test, a deterministic test sequence followed by a pseudo-random one. This scheme allows the maximum fault coverage detection to be achieved, furthermore the silicon area overhead of the mixed hardware generator can be reduced.

• Transactions of the Korean Society of Mechanical Engineers B
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• v.33 no.7
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• pp.541-551
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• 2009

Configuration of the inlet transition square duct (hereinafter referred to as "transition duct") for heat recovery steam generator (hereinafter referred to as "HRSG") in combined cycle power plant is limited by the construction type of HRSG and plant site condition. The main purpose of the present study is to analyze the effect of a variation in turbulent flow pattern by roof slop angle change of transition duct for horizontal HRSG, which is influencing heat flux in heat transfer structure to the finned tube bank. In this study, a computational fluid dynamics(CFD) is applied to predict turbulent flow pattern and comparisons are made to 1/12th scale cold model test data for verification. Re-normalization group theory (RNG) based k-$\epsilon$ turbulent model, which improves the accuracy for rapidly strained flow and swirling flow in comparison with standard k-$\epsilon$ model, is used for the results cited in this study. To reduce the amount of computer resources required for modeling the finned tube bank, a porous media model is used.