• New & Renewable Energy
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• v.5 no.3
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• pp.4-12
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• 2009

The effect of change in DFIG (doubly-fed wind power generator) rotating speed and active power on the grid was analyzed to understand the characteristics of wind power using the wind power simulator connected to the grid at Gochang Power Quality Test Center. Electric power quality improvement devices (DVR, STATCOM, SSTS) and electric power quality disturbance application devices for 22.9 kV grid are equipped at Gochang Power Quality Test Center. Induction motor and VVVF inverter were used to emulate the blade of a wind power generator, and a simulator for Cage wound induction generator and DFIG was developed. The trial line were assumed to be 20 km and 40 km in length, and variable wind speed pattern was set using wind speed data from Ducjeokdo to verify the power characteristics of the wind power generator according to rotating speed.

• Proceedings of the KIEE Conference
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• 1998.11b
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• pp.600-602
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• 1998

In this paper, we implement BIST to efficiently test circuits with pipeline architecture and JTAG to control implemented BIST and support board level test. Since implemented BIST is designed to be initialized using new seed, hard-to-detect faults are easily detected. Besides, to optimize area overhead, it uses JTAG instead of BIST controller and modified pipeline register instead of added test pattern generator and signature generator. And, to optimize pin overhead, it uses pins of JTAG. Function and efficiency of implemented BIST is verified by simulation.

• Journal of the Korean Society for Precision Engineering
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• v.19 no.11
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• pp.103-111
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• 2002

In this study, the natural flaws in welding parts are classified using the signal pattern classification method. The storage digital oscilloscope including FFT function and enveloped waveform generator is used and the signal pattern recognition procedure is made up the digital signal processing, feature extraction, feature selection and classifier design. It is composed with and discussed using the distance classifier that is based on euclidean distance the empirical Bayesian classifier. feature extraction is performed using the class-mean scatter criteria. The signal pattern classification method is applied to the signal pattern recognition of natural flaws.

• Proceedings of the KIEE Conference
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• 2006.07b
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• pp.935-936
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• 2006

This paper deals with a 3-phase voltage disturbance generator. The proposed generator can be used for the performance teat of custom power devices with nonlinear load characteristics as well as linear load. The principle of the voltage sag, swell, outage, and unbalance generation is described. The switching pattern for the SCR thyristors in each mode is analysed to guarantee the system reliability. The validity of the proposed scheme is verified through simulation result.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.8
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• pp.29-35
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• 2010

In this paper we propose a new pattern generator for a BIST architecture that can reduce the power consumption during test application. The principle of the proposed method is to reconstruct an LFSR circuit to reduce WSAs of the heavy nodes by suppressing the heavy inputs. We propose algorithms for finding heavy nodes and heavy inputs. Using the Modified LFSR which consists of some AND/OR gates trees and an original LFSR, BIST applies modified test patterns to the circuit under test. The proposed BIST architecture with small hardware overhead effectively reduces the average power consumption during test application while achieving high fault coverage. Experimental results on the ISCAS benchmark circuits show that average power reduction can be achieved up to 30.5%.

• The Transactions of the Korea Information Processing Society
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• v.7 no.10
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• pp.3226-3235
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• 2000

The more complex and larger semiconductor integraed circuits become, the core important delay test becomes which guarantees that semiconductor integrated circuits operate in time. In this paper, we propose a new partial enhanced scan method that can generate test patterns for path delay faults offectively. We implemented a new partial enhanced scan method based on an automatic test pattern generator(ATPG) which uses implication and justification . First. we generate test patterns in the standard scan environment. And if test patterns are not generated regularly in the scan chain, we determine flip-flops which applied enhanced scan flip-flops using the information derived for running an automatic test pattern generator inthe circuti. Determming enhanced scan flip-flops are based on a fault coverage or a hardware overhead. through the expenment for JSCAS 89 benchmark sequential circuits, we compared the fault coverage in the standard scan enviroment and enhance scan environment, partial enhanced scan environment. And we proved the effectiveness of the new partial enhanced scan method by identifying a high fault coverage.

• Transactions of the Korean Society of Mechanical Engineers B
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• v.29 no.6 s.237
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• pp.755-762
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• 2005

To evaluate the aerodynamic efficiency of TR-S2 configuration designed by SUDC, wind tunnel tests of $40\%$ scaled model were done in KARI LSWT. The aerodynamic characteristics of plain and Semi-Slotted Flaperon were compared, and vortex generators were installed to improve flow pattern along the wing surface. Effects of the control surface such as elevator, rudder, aileron, and incidence angle of horizontal tail are measured for various testing conditions. Test results showed that Semi-Slotted Flaperon produced more favorable lift, lift/drag, and stall margins and application of vortex generator would be best choice to enhance wing performance. Longitudinal, lateral and directional characteristics of TR-S2 were found to be stable for the pitch and yaw motions.

• Proceedings of the KIEE Conference
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• 2002.07c
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• pp.1846-1849
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• 2002

A shorted-turn test was performed at the Sininchon combined cycle power plant on gas turbine generators. The test was conducted using a permanent flux probe and on-line diagnosis system. The flux probe installed in the generator air gap senses the field winding slot leakage flux and produces a voltage proportional to the rate of change of the flux. This pattern of flux variation is a signature unique to each field winding. We have also applied a voltage waveform analysis technique that can identify the pole location, slot number and number of shorted-turn with each slot.

• Proceedings of the KIEE Conference
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• 2007.07a
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• pp.192-194
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• 2007

This paper proposes a new wind turbine simulator using a squirrel cage induction for control performance test of DFIG (doubly-fed induction generator). The turbine static characteristics are modeled using the relation between the turbine torque versus the wind speed and the blade pitch angle. The turbine performance is subjected to a real wind speed pattern by modeling the wind speed as a sum of harmonics with a wide range of frequency. The turbine model includes the effect of the tower shadow and wind shear. A pitch angle controller is designed and used to protect the coupled generator by limiting the turbine speed to the maximum value. Experimental results are provided for a 3[kW] wind turbine simulator at laboratory.

• The Transactions of the Korea Information Processing Society
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• v.6 no.6
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• pp.1656-1666
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• 1999

The more complex and large digital circuits become, the more important delay test becomes which guarantees that circuits operate in time. In this paper, the proposed algorithm is developed, which enable the fast indirect implication for efficient test pattern generation in sequential circuits of standard scan environment. Static learning algorithm enables application of a new implication value using contrapositive proposition. The static learning procedure found structurally, analyzes the gate structure in the preprocessing phase and store the information of learning occurrence so that it can be used in the test pattern generation procedure if it satisfies the implication condition. If there exists a signal line which include all paths from some particular primary inputs, it is a partitioning point. If paths passing that point have the same partial path from primary input to the signal or from the signal to primary output, they will need the same primary input values which separated by the partitioning point. In this paper test pattern generation can be more effective by using this partitioning technique. Finally, an efficient delay fault test pattern generator using indirect implication is developed and the effectiveness of these algorithms is demonstrated by experiments.