• Title/Summary/Keyword: test circuit

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A Study on LCL Circuit for Satellite Power System Applying WBG Device (WBG 소자를 적용한 위성 전력 시스템용 LCL 회로에 관한 연구)

  • Yoo, Jeong Sang;Ahn, Tae Young;Gil, Yong Man;Kim, Hyun Bae;Park, Sung Woo;Kim, Kyu Dong
    • Journal of the Semiconductor & Display Technology
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    • v.21 no.2
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    • pp.101-106
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    • 2022
  • In this paper, WBG semiconductor such as SiC and GaN were applied as power switches for LCL circuit that can be applied to satellite power systems and the test results of the LCL circuit are reported. P-channel MOSFET and N-channel MOSFET, which were generally used in the conventional LCL circuit, were applied together to expand the utility of the test results. The design and stability evaluation were performed using a Micro Cap circuit simulation program. For the test circuit, a module using each switch was manufactured, and a total of 5 modules were manufactured and the steady state and transient state characteristics were compared. From the experimental results, the LCL circuit for power supply of the satellite power system constructed in this paper satisfied the constant current and constant voltage conditions under various operating conditions. The P-channel MOSFET showed the lowest efficiency characteristics, and the three N-channel switches of Si, SiC and GaN showed relatively high efficiency characteristics of up to 99.05% or more. In conclusion, it was verified that the on-resistor of the switch had a direct effect on the efficiency and loss characteristics.

Phase Detector Design for Inspection of a RLC Parallel Circuit on the Electronic Circuit Board (전자회로 보오드의 RLC 병렬회로 검사를 위한 위상검출회로 설계)

  • Han, Kil-Hee;Lee, Kyoung-Ho;Lim, Chul-Soo;Choi, Bung-Gun;Ko, Yun-Seok
    • Proceedings of the KIEE Conference
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    • 2002.04a
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    • pp.183-185
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    • 2002
  • This paper proposes the test method for the testing of a RLC parallel circuit on the electronic circuit board. This method utilizes a guarding circuit and a phase detection circuit. The guarding circuit separates electrically the tested device or circuit from printed circuit board. Phase detector estimates the phase difference from two signals, voltage and current. This method computes R. L and C value from phase difference($\theta$) and impedance value(Z) obtained by enforcing two other frequence stimulus under the guarding state.

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Study on the analysis of impulse test wave in the short coil (layer)of transformer winding (변압기 권선(층간)단락시의 충격파시험파형분석에 관한 연구)

  • 박민호
    • 전기의세계
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    • v.25 no.5
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    • pp.75-78
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    • 1976
  • The most difficult problem encountered in impulse test of transformer is the determination of exact fauly for coil layer short. This paper is to establish one of improved standards in the above case by means of wave form analysis, based on the equivalent circuits and experimental investigation. During the fault occurs, the local oscillation in fault circuit is applicable where as the reflection wave is utilized to the main circuit. The result current wave form at neutral impeadance point is similar to the wave form by impulse test and has the singular wave form respectively.

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A Test Vector Reordering for Switching Activity Reduction During Test Operation Considering Fanout (테스트시 스위칭 감소를 위해 팬 아웃을 고려한 테스트벡터 재 정렬)

  • Lee, Jae-Hoon;Baek, Chul-Ki;Kim, In-Soo;Min, Hyoung-Bok
    • The Transactions of The Korean Institute of Electrical Engineers
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    • v.60 no.5
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    • pp.1043-1048
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    • 2011
  • Test vector reordering is a very effective way to reduce power consumption during test application. But, it is time-consuming and complicated processes, and it does not consider internal circuit structure, which may limit the effectiveness. In this paper, we order test vectors using fanout count of primary inputs that consider the internal circuit structure, which may reduce the switching activity. Then, we reorder test test vectors again by using Hamming distance between test vectors. We proposed FOVO algorithm to perform these two ideas. FOVO is an effective way to reduce power consumption during test application. The algorithm is applied to benchmark circuits and we get an average of 3.5% or more reduction of the power consumption.

Universal Test Set Generation for Multi-Level Test of Digital CMOS Circuits (디지털 CMOS 회로의 Multi-Level Test를 위한 범용 Test Set 생성)

  • Dong Wook Kim
    • Journal of the Korean Institute of Telematics and Electronics A
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    • v.30A no.2
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    • pp.63-75
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    • 1993
  • As the CMOS technology becomes the most dominant circuit realization method, the cost problem for the test which includes both the transistor-level FET stuck-on and stuck-off faults and the gatelevel stuck-at faults becomes more and more serious. In accordance, this paper proposes a test set and its generation algorithm, which handles both the transistor-level faults and the gate-level faults, thus can unify the test steps during the IC design and fabrication procedure. This algorithm uses only the logic equation of the given logic function as the input resource without referring the transistor of gate circuit. Also, the resultant test set from this algorithm can improve in both the complexity of the generation algorithm and the time to apply the test as well as unify the test steps in comparing the existing methods.

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The Study of the Verification Test for Development of Contacts(50kA) of Making Switch and Back Up Breaker (대용량(50kA)의 Making Switch와 Back Up Breaker 접점 개발에 따른 검증시험의 연구)

  • Kim Sun-Koo;Kim Won-Man;La Dae-Ryeol;Roh Chang-Il;Lee Dong-Jun;Jung Heung-Soo
    • Proceedings of the KIEE Conference
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    • summer
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    • pp.842-844
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    • 2004
  • The Back Up Breaker and Making Switch are very important equipments for the short circuit test facility, and contacts are the most important parts of the above switches. There are very many kind of contacts according to switches characteristic and should be done the verification test before use, especially development contacts. This study describes the class of switches, arc chute, material of whole contacts and essential test for verification. The essential test for verification are dielectric test, mechanical operation test, short-time withstand current test, load current breaking test, and short-circuit making current test etc.

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Use of an Electric Muscle Stimulation Thigh Band and High-intensity Circuit Training to Activate the Thigh Muscle (무릎 밴드를 이용한 EMS와 High-intensity Circuit Training의 대퇴근육 활성화 효과)

  • Hanna Park;Jinhee Park;Jooyong Kim
    • Journal of Fashion Business
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    • v.27 no.2
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    • pp.39-51
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    • 2023
  • The purpose of this study was to effectively improve the thigh muscles of adult women working from home due to COVID-19. In this study, ten adult women working from home performed 1) an electromyography test, 2) a static balance test on a balance board, and a 3) dynamic balance test by squatting on a Bosu ball four times: before electric muscle stimulation (EMS), after EMS, after high-intensity circuit training (HICT), and after EMS plus HICT. For this test, EMS was attached to a medical knee support to manufacture an EMS knee band that could be easily worn regardless of the location. For the experiment, EMS(electric muscle stimulation) was attached to the medical knee protector to manufacture an EMS knee band that can be easily worn regardless of location, and was measured based on the right foot. The study results confirmed that in all tests (electromyography test, static balance test on the balance board, and dynamic balance test by squatting on a Bosu ball), thigh strength improved in the order of treatment before EMS, after EMS, after HICT, and after EMS plus HICT. The study showed that people working from home or with activity restrictions due to COVID-19 had better exercise effects when wearing the EMS knee band and performing HICT, even in a small space.

Performance Test Circuit and Control Method for Submodule of MMC-HVDC System (MMC-HVDC 시스템용 서브모듈 성능시험회로와 제어기법)

  • Jo, Kwang-Rae;Seo, Byuong-Jun;Park, Kwon-Sik;Kim, Hak-Soo;Heo, Jin-Yong;Nho, Eui-Cheol
    • The Transactions of the Korean Institute of Power Electronics
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    • v.24 no.6
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    • pp.452-458
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    • 2019
  • This study proposes a new test circuit and control method for the submodules of modular multilevel converter (MMC)-based HVDC systems. The test current of conventional submodule test circuits cannot provide the DC offset components or may have some distortion in the linearized current with the DC offset. The proposed scheme can provide not only the DC component but also linearized current without distortion. Therefore, the submodule test current waveform is relatively similar to that of a real submodule consisting of an MMC-based HVDC system. The validity of the proposed circuit and control method is verified through a simulation and experiment.

The Intrinsic Safety Evaluation of Solar Photovoltaic Cell (태양전지셀의 본질안전 방폭성능 평가)

  • Lee, Chun-Ha;Jee, Seung-Wook;Kim, Si-Kuk
    • Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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    • v.25 no.7
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    • pp.49-54
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    • 2011
  • Now the world will regulate the CO2 emission due to environmental issues. For an alternative plan photovoltaic system is watched. So, photovoltaic system is trend of big city and it is mandatory for renovation of construction. Oil & gas filling station existed in city is suitable to found the photovoltaic system. But the general photovoltaic system in oil & gas filling station is difficult to found because it is classified into hazardous area. This paper evaluates intrinsic safety evaluation of solar cell for making basic data to found for the photovoltaic system on hazardous area. The intrinsic safety characteristic is evaluated by short-circuit ignition test using IEC type spark ignition test apparatus and temperature rising test. The result of short-circuit ignition test, propane-air mixture gas is exploded on condition that 4 solar cells(9[V], 90[mA]) are connected serially under insolation 800[W/$m^2$]. So, if a larger solar module will be used at oil & gas filling station than we were tested, it needs explosion proof. As the result of rising temperature test, the temperature rising due to short circuit is not so much, but when the temperature rises due to radiant heat, it demands careful consideration for environmental influence.

Immunity Test for Semiconductor Integrated Circuits Considering Power Transfer Efficiency of the Bulk Current Injection Method

  • Kim, NaHyun;Nah, Wansoo;Kim, SoYoung
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.14 no.2
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    • pp.202-211
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    • 2014
  • The bulk current injection (BCI) and direct power injection (DPI) method have been established as the standards for the electromagnetic susceptibility (EMS) test. Because the BCI test uses a probe to inject magnetically coupled electromagnetic (EM) noise, there is a significant difference between the power supplied by the radio frequency (RF) generator and that transferred to the integrated circuit (IC). Thus, the immunity estimated by the forward power cannot show the susceptibility of the IC itself. This paper derives the real injected power at the failure point of the IC using the power transfer efficiency of the BCI method. We propose and mathematically derive the power transfer efficiency based on equivalent circuit models representing the BCI test setup. The BCI test is performed on I/O buffers with and without decoupling capacitors, and their immunities are evaluated based on the traditional forward power and the real injected power proposed in this work. The real injected power shows the actual noise power level that the IC can tolerate. Using the real injected power as an indicator for the EMS test, we show that the on-chip decoupling capacitor enhances the EM noise immunity.