• Journal of the Korean Institute of Telematics and Electronics D
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• v.35D no.2
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• pp.78-85
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• 1998

The design method of a temperature stable bandpass filter using dielectric coaxial resonators of with two dielectric ceramics with opposite signs of temperature coefficient of dielectric constant (${\tau}_{\epsilon}$) to compensate for each other in this method. $MgTiO_3$(${\tau}_{\epsilon}$=+99 ppm/${\circ}C$) as a positive ${\tau}_{\epsilon}$ material and Ba($Zn_{1/3}Nb_{2/3}$)$O_3$(${\tau}_{\epsilon}$=-77ppm/${\circ}C$) as a negative material were selected. The length of a SIR for the temperature stability was calculated according to the design method and the susceptance slope parameter of the SIR was obtained. A temperature stable bandpass filter using dielectric SIR's was designed, simulated and fabricated. The center frequency of this filter was 915 MHz and the pass bandwidth was 20 MHz. Temperature properties of this bandpass filter by simulations were compared with the measured results of the bandpass filter fabricated.

• Journal of the Korean Institute of Telematics and Electronics S
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• v.35S no.8
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• pp.96-105
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• 1998

The aim of this paper is to propose the method of WDHMM(Weighted DHMM), using the MLP-VQ for the improvement of speaker-independent connect-digit recognition system. MLP neural-network output distribution shows a probability distribution that presents the degree of similarity between each pattern by the non-linear mapping among the input patterns and learning patterns. MLP-VQ is proposed in this paper. It generates codewords by using the output node index which can reach the highest level within MLP neural-network output distribution. Different from the old VQ, the true characteristics of this new MLP-VQ lie in that the degree of similarity between present input patterns and each learned class pattern could be reflected for the recognition model. WDHMM is also proposed. It can use the MLP neural-network output distribution as the way of weighing the symbol generation probability of DHMMs. This newly-suggested method could shorten the time of HMM parameter estimation and recognition. The reason is that it is not necessary to regard symbol generation probability as multi-dimensional normal distribution, as opposed to the old SCHMM. This could also improve the recognition ability by 14.7% higher than DHMM, owing to the increase of small caculation amount. Because it can reflect phone class relations to the recognition model. The result of my research shows that speaker-independent connected-digit recognition, using MLP-VQ and WDHMM, is 84.22%.

• Journal of the Korean Institute of Telematics and Electronics
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• v.18 no.3
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• pp.42-51
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• 1981

Boron was predeposited into p (100) Si wafer at 94$0^{\circ}C$ for 60minutes to make the back surface field. High tempreature diffusion process at 1145$^{\circ}C$ for 3 hours was immediately followed without removing boron glass to obtain high surface concentration Back boron was annealed at 110$0^{\circ}C$ for 40minutes after boron glass was removed. N+ layer was formed by predepositing with POCI3 source at 90$0^{\circ}C$ for 7~15 minutes and annealed at 80$0^{\circ}C$ for 60min1es under dry Of ambient. The triple metal layers were made by evaporating Ti, Pd, Ag in that order onto front and back of diffused wafer to form the front grid and back electrode respectively. Silver was electroplated on front and back to increase the metal thickness form 1~2$\mu$m to 3~4$\mu$m and the metal electrodes are alloyed in N2 /H2 ambient at 55$0^{\circ}C$ and followed by silicon nitride antireflection film deposition process. Under artificial illumination of 100mW/$\textrm{cm}^2$ fabricated N+PP+ cells showed typically the open circuit voltage of 0.59V and short circuit current of 103 mA with fill factor of 0.80 from the whole cell area of 3.36$\textrm{cm}^2$. These numbers can be used to get the actual total area(active area) conversion efficiency of 14.4%(16.2%) which has been improved from the provious N+P cell with 11% total area efficiency by adding P+ back.

• Journal of Korea Spatial Information System Society
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• v.8 no.2 s.17
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• pp.109-120
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• 2006

This paper addresses techniques for predicting a future path of an object moving on a road network. Most prior methods for future prediction mainly focus their attention on objects moving in Euclidean space. A variety of applications such as telematics, however, deal with objects that move only over road networks in most cases, thereby requiring an effective method of future prediction of moving objects on road networks. In this paper, we propose a novel method for predicting a future path of an object by analyzing past trajectories whose changing pattern is similar to that of a current trajectory of a query object. We devise a new function that measures a similarity between trajectories by reflecting the characteristics of road networks. By using this function, we predict a future path of a given moving object as follows: First, we search for candidate trajectories that contain subtrajectories similar to a given query trajectory by accessing past trajectories stored in moving object databases. Then, we predict a future path of a query object by analyzing the moving paths along with a current position to a destination of candidate trajectories thus retrieved. Also, we suggest a method that improves the accuracy of path prediction by regarding moving paths that have just small differences as the same group.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.6
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• pp.39-47
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• 1998

A fourth-order $\Sigma$-$\Delta$ modulator is designed and implemented in 0.6 $\mu\textrm{m}$ CMOS technology. The modulator is verified by introducing nonlinear factors such as DC gain and slew rate in system model that determines the transfer function in S-domain and in time-domain. Dynamic range is more than 110 dB and the peak SM is 102.6 dB at a clock rate of 2.8224 MHz for voiceband signal. The structure of a ∑-$\Delta$ modulator is a modified fourth-order ∑-$\Delta$ modulator using direct feedback loop method, which improves performance and consumes less power. The transmission zero for noise is located in the first-second integrator loop, which reduces entire size of capacitors, reduces the active area of the chip, improves the performance, and reduces power dissipation. The system is stable because the output variation with respect to unit time is small compared with that of the third integrator. It is easy to implement because the size of the capacitor in the first integrator, and the size of the third integrator is small because we use the noise reduction technique. This paper represents a new design method by modeling that conceptually decides transfer function in S-domain and in Z-domain, determines the cutoff frequency of signal, maximizes signal power in each integrator, and decides optimal transmission-zero frequency for noise. The active area of the prototype chip is 5.25$\textrm{mm}^2$, and it dissipates 10 mW of power from a 5V supply.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.11
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• pp.21-30
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• 1998

In this paper, a digital current control system using a FPGA(Field Programmable Gate Array) was implemented, and the system was applied to an induction motor widely used as an industrial driving machine. The FPGA designed by VHDL(VHSIC Hardware Description Language) consists of a PWM(Pulse Width Modulation) generation block, a PWM protection block, a speed measuring block, a watch dog timer block, an interrupt control block, a decoder logic block, a wait control block and digital input and output blocks respectively. Dedicated clock inputs on the FPGA were used for high-speed execution, and an up-down counter and a latch block were designed in parallel, in order that the triangle wave could be operated at 40 MHz clock. When triangle wave is compared with many registers respectively, gate delay occurs from excessive fan-outs. To reduce the delay, two triangle wave registers were implemented in parallel. Amplitude and frequency of the triangle wave, and dead time of PWM could be changed by software. This FPGA was synthesized by pASIC 2SpDE and Synplify-Lite synthesis tool of Quick Logic company. The final simulation for worst cases was successfully performed under a Verilog HDL simulation environment. And the FPGA programmed for an 84 pin PLCC package was applied to digital current control system for 3-phase induction motor. The digital current control system of the 3 phase induction motor was configured using the DSP(TMS320C31-40 MHz), FPGA, A/D converter and Hall CT etc., and experimental results showed the effectiveness of the digital current control system.

• Journal of the Korean Institute of Telematics and Electronics S
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• v.36S no.6
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• pp.17-29
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• 1999

In this paper, the prioritized queueing handoff scheme in CDMA (Code Division Multiple Access) cellular system is proposed. Also, the analytical survey for the proposed scheme is carried out, and the performance of this scheme is compared with that of non prioritized scheme and FIFO (First In First Out) queue scheme by computer simulation. The handoff region is defined as the time between the handoff treshold and the receiver threshold, and it is used for the maximum queue waiting time in the proposed scheme. The handoff and the receiver thresholds are defined as rewpectively: 1) the time that the Pilot Strength Measurement Message in the neighbor in the neighbor cell is received to the BS (Base Station) under the T_ADD threshold; and 2) the time that the T_DROP timer is expired and the Pilot Strength Measurement Message in the current cell is received to the BS under the T_DROP threshold. The performance metrics for analyzing the proposed scheme are : 1) probability of forced termination; 2) probability of call blocking; 3) ratio of carried traffic to total offered load; 4) average queue size; 5) average handoff delay time in queue. The simulation results show that the proposed scheme maintains high performance for handoff requests at a small penalty in total system capacity.

• Journal of the Korean Institute of Telematics and Electronics S
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• v.36S no.2
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• pp.69-80
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• 1999

Recently, social requirements of personal identification techniques are rapidly expanding in a number of new application ares. Especially fingerprint recognition is the most important technology. Fingerprint recognition technologies are well established, proven, cost and legally accepted. Therefore, it has more spot lighted among the any other biometrics technologies. In this paper we propose a new on-line fingerprint recognition algorithm for non-inked type live scanner to fit their increasing of security level under the computing environment. Fingerprint recognition system consists of two distinct structural blocks: feature extraction and feature matching. The main topic in this paper focuses on the feature matching using the fingerprint minutiae (ridge ending and bifurcation). Minutiae matching is composed in the alignment stage and matching stage. Success of optimizing the alignment stage is the key of real-time (on-line) fingerprint recognition. Proposed alignment algorithm using clique shows the strength in the search space optimization and partially incomplete image. We make our own database to get the generality. Using the traditional statistical discriminant analysis, 0.05% false acceptance rate (FAR) at 8.83% false rejection rate (FRR) in 1.55 second average matching speed on a Pentium system have been achieved. This makes it possible to construct high performance fingerprint recognition system.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.36D no.12
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• pp.37-42
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• 1999

In this paper, some of main processes for the next generation integrated circuits, such as Cu damascene process using CMP, electron beam lithography, $SiO_2$ CVD and RIE, Ti/Cu-CVD were carried cut and then, two level Cu interconnects were accomplished. In the results of CMP unit processes, a 4,635 ${\AA}$/min of removal rate, a selectivity of Cu : $SiO_2$ of 150:1, a uniformity of 4.0% are obtained under process conditions of a head pressure of 4 PSI, table and head speed of 25rpm, a oscillation distance of 40 mm, and a slurry flow rate of 40 ml/min. Also 0.18 ${\mu}m\;SiO_2$ via-line patterns are fabricated using 1000 ${\mu}C/cm^2$ dose, 6 minute and 30 second development time and 1 minute and 30 second etching time. And finally sub-0.2 ${\mu}$ twolevel metal interconnects using the developed processes were fabricated and the problems of multilevel interconnects are discussed.

• Journal of the Korean Institute of Telematics and Electronics S
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• v.36S no.2
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• pp.96-107
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• 1999

The generalized sidelobe cancellers(GSC's) ar used for suppressing an interference in array radar. The frequency-domain GSC's have a faster convergence rate than the time-domain GSC's because they remove the correlation between the interferences using a frequency-domain least mean square(LMS) algorithm. However, we have not fully used the advantage of the frequency-domain GSC's since we have always updated the weights of all frequency bins, even the interferer free frequency bin. In this paper, we propose a new frequency-domain GSC based on constant false-alarm rate(CFAR) detector, of which GSC adaptively determine the bin whose weight is updated according to the power of each frequency bin. This canceller updates the weight of only updated according to the power of each frequency bin. This canceller updates the weight of only the bin of which the power is high because of the interference signal. The computer simulation shows that the new GSC reduces the iteration number for convergence over the conventional GSC's by more than 100 iterations. The signal-to-noise ration(SNR) improvement is more than 5 dB. Moreover, the number of renewal weights required for the adaptation is much fewer than that of the conventional one.